Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1987-12-11
1989-08-15
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
365154, 365174, 36518912, G11C 700
Patent
active
048581917
ABSTRACT:
A semiconductor integrated circuit includes an input buffer circuit, a decoder circuit and a plurality of memory cells. Each of the input buffer circuit and the decoder circuit consists of a combination of bipolar transistors and MOS transistors. In this combination various measures are taken to increase the operation speed and to reduce the electric power consumption. In an example thereof the data line load for the memory cells is constituted by Schottky barrier type diodes. In another example the load used for the respective emitter follower transistors is constituted by an MOS transistor operating as a variable resistance.
In still another example, in a CMOS NOR circuit of the decoder circuit the number of P channel MOS transistors are fewer than the number of N channel MOS transistors.
REFERENCES:
ISSC Digest of Technical Papers "Static Rams" Hudson et al., Feb. 12, 1982, pp. 248-249.
Higuchi Hisayuki
Homma Noriyuki
Suzuki Makoto
Fears Terrell W.
Hitachi , Ltd.
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