Electronic digital logic circuitry – Significant integrated structure – layout – or layout... – Field-effect transistor
Reexamination Certificate
2008-12-09
2010-11-30
Barnie, Rexford N (Department: 2819)
Electronic digital logic circuitry
Significant integrated structure, layout, or layout...
Field-effect transistor
C257S208000, C257S371000, C331S057000
Reexamination Certificate
active
07843227
ABSTRACT:
The present invention is directed to reduce the chip area of a semiconductor integrated circuit. A semiconductor integrated circuit of the invention includes a first transistor, a second transistor disposed adjacent to the first transistor along a Y axis, and a third transistor disposed adjacent to the second transistor along an X axis. The semiconductor integrated circuit further includes a fourth transistor disposed adjacent to the third transistor along the Y axis and disposed adjacent to the first transistor along the X axis. The first to fourth transistors share a well, and an output signal of the first transistor and an output signal of the second transistor have phases opposite to each other. An output signal of the second transistor and an output signal of the third transistor have phases opposite to each other. An output of the third transistor and an output signal of the fourth transistor have phases opposite to each other. The outputs of the transistors act so as to cancel out fluctuations in well potential.
REFERENCES:
patent: 2007/0063288 (2007-03-01), Furuta et al.
patent: 2008/0142898 (2008-06-01), Watanabe et al.
patent: 2003-309178 (2003-10-01), None
patent: 2004-319855 (2004-11-01), None
Barnie Rexford N
Miles & Stockbridge P.C.
Renesas Electronics Corporation
Tran Jany
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