Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

2007-11-06

2007-11-06

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S726000, C714S727000

Reexamination Certificate

active

11206948

ABSTRACT:
The number of S-FFs in a scan-path is decreased by half and a test time needed is decreased. An I/O terminal1A is connected to a scan-path31-3mand a combination circuit2via a selector5A and an output of the scan-path31-3mis connected to an I/O terminal1B via a selector6A and a tri-state buffer7A. The I/O terminal1B is connected to a scan-path3m+1-3nand to the combination circuit2via a selector5B and the output of the scan-path3m+1-3nis connected to the I/O terminal1A via a selector6B and tri-state buffer7B. When testing, the tri-state buffers are turned off and test-data are supplied by connecting the I/O terminal1A,1B to the scan-path31-3m, 3m+1-3nrespectively. Thereafter, output signals of the combination circuit is applied to each S-FF3,and the test data are read out from the I/O terminal1A,1B by turning on the each tri-state buffer7A,7B.

REFERENCES:
patent: 2003/0226083 (2003-12-01), Yamanaka et al.
patent: 2004/0181723 (2004-09-01), Nakao et al.
patent: 2004/0250185 (2004-12-01), Date
patent: 5-142298 (1993-06-01), None
patent: 2002-009238 (2002-01-01), None

Affiliated with

Also associated with

Rating

Semiconductor integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3867766