Semiconductor integrated circuit

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay

Reexamination Certificate

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C713S400000, C713S500000, C713S501000, C327S149000, C327S150000, C327S156000, C327S157000, C327S291000, C327S293000, C327S299000, C365S189011, C365S189050, C365S191000, C365S194000

Reexamination Certificate

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10768441

ABSTRACT:
A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input terminal for receiving a clock signal; a data input terminal for receiving a data signal; internal clock generating circuits for generating an internal clock signal which is switched at an intermediate timing between the i-th (i: an integer of 1 or larger) switch timing and the (i+1)th switch timing of the clock signal; and a latch circuit for latching the data signal synchronously with the internal clock signal. An internal clock signal which is switched at an intermediate timing between the i-th switch timing and the (i+1)th switch timing of the clock signal is generated, and the data signal is fetched synchronously with the internal clock signal.

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patent: 7057431 (2006-06-01), Kwak
patent: 11-110062 (1999-04-01), None

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