Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2007-02-13
2007-02-13
Clark, Jasmine (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S522000, C257S691000, C257S735000, C257S736000, C257SE23010, C257SE23079, C324S765010
Reexamination Certificate
active
11105482
ABSTRACT:
To provide a test technology capable of reducing a package size by reducing a number of terminals (pins) in a semiconductor integrated circuit of SIP or the like constituted by mounting a plurality of semiconductor chips to a single package, in SIP102constituted by mounting a plurality of semiconductor chips to a signal package of ASIC100,SDRAM101and the like, a circuit of testing SDRAM101(SDRAMBIST109) is provided at inside of ASIC100,and SDRAM101is tested from outside of SDRAM101,that is, from ASIC100.By providing the test circuit of SDRAM101at inside of ASIC100,it is not necessary to extrude a terminal for testing SDRAM101to outside of SIP102.
REFERENCES:
patent: 5808877 (1998-09-01), Jeong et al.
patent: 6492719 (2002-12-01), Miyamoto et al.
patent: 06-151685 (1994-05-01), None
patent: 09-160802 (1997-06-01), None
patent: 10-123212 (1998-05-01), None
Ito Fujio
Kikuchi Takafumi
Sakamoto Noriaki
Sato Tomoru
Yokohama Takehisa
Antonelli, Terry Stout and Kraus, LLP.
Clark Jasmine
Renesas Technology Corp.
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