Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2006-06-06
2006-06-06
Decady, Albert (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S733000, C365S201000
Reexamination Certificate
active
07058863
ABSTRACT:
A semiconductor integrated circuit including a region of a memory macro function block is divided into memory core function block and interface function block regions. The interface function block includes a test circuit, a command decoder for a test, an address decoder for the test, a memory core input/output circuit which inputs a command and address into the memory core function block and transmits!receives data with the memory core function block, a configuration memory block in which information of a memory capacity of the memory core function block and configuration of a memory core is stored, and a configuration memory block which controls a data path and address path of the memory core function block based on the stored information.
REFERENCES:
patent: 5308798 (1994-05-01), Brasen et al.
patent: 5450364 (1995-09-01), Stephens et al.
patent: 5825783 (1998-10-01), Momohara
patent: 5910181 (1999-06-01), Hatakenaka et al.
patent: 6046957 (2000-04-01), Shyu
patent: 6052806 (2000-04-01), Beat
patent: 6173356 (2001-01-01), Rao
patent: 6182253 (2001-01-01), Lawrence et al.
patent: 6260127 (2001-07-01), Olarig et al.
patent: 6405358 (2002-06-01), Nuber
patent: 6446159 (2002-09-01), Kai et al.
patent: 6467056 (2002-10-01), Satou et al.
patent: 6543039 (2003-04-01), Watanabe
patent: 6553526 (2003-04-01), Shephard, III
patent: 6813599 (2004-11-01), Court et al.
patent: 6829728 (2004-12-01), Cheng et al.
patent: 1163475 (1997-10-01), None
patent: 1234901 (1999-11-01), None
patent: 9-145790 (1997-06-01), None
patent: 10-302476 (1998-11-01), None
“Merged DRAM-Logic in the Year 2001”, Diodato et al., Aug. 24-25, 1998, Memory Workshop, Design and Testing, 1998 IEEE, pp. 24-30.
Kouchi Toshiyuki
Numata Kenji
Takahashi Makoto
De'cady Albert
Trimmings John P.
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