Semiconductor integrated circuit

Details Semiconductor integrated circuit Semiconductor integrated circuit

1999-01-05

2002-04-09

Moise, Emmanuel L. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S726000, C714S733000

Reexamination Certificate

active

06370663

ABSTRACT:

BACKGROUND THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more specifically to a semiconductor integrated circuit having an improved efficiency in a function test for a plurality of circuit blocks each realizing a predetermined function.
2. Description of Related Art
With a recent scale-up of a semiconductor integrated circuit, a plurality of circuit blocks for realizing various functions have been incorporated in a single semiconductor integrated circuit. These circuit blocks are interconnected to function as one semiconductor integrated circuit. On the other hand, the semiconductor integrated circuit has a plurality of input terminals and a plurality of output terminals for interface with an external of the semiconductor integrated circuit.
In addition, each of circuit blocks has a plurality of input nodes and a plurality of output nodes so that the circuit blocks are interconnected in the inside of the semiconductor integrated circuit. However, the circuit blocks cannot be controlled and observed directly at the input terminals and the output terminals of the semiconductor integrated circuit.
Nevertheless, it is necessary to verify whether or not all functions of the circuit blocks operate normally. For this purpose, it is necessary to supply a predetermined signal from the input terminals of the semiconductor integrated circuit to the respective circuit blocks and to observe the result of the operation of each circuit block at the output terminals of the semiconductor integrated circuit.
In the prior art, as a means for verifying the function of the circuit blocks, there is a means for directly connecting the input terminals and the output terminals of the semiconductor integrated circuit to the input nodes and the output nodes of any selected circuit block. However, this means requires a plurality of multiplexers and a number of interconnections, with the result that the circuit scale of the semiconductor integrated circuit inevitably becomes large.
In addition, a scan-path test is known, in which, in a test mode, all flipflops included in the semiconductor integrated circuit are cascade-connected by switching over multiplexers, so as to constitute one long shift register, and after a predetermined signal is given from the input terminal of the semiconductor integrated circuit to the shift register composed of the cascade-connected flipflops, an internal condition of the semiconductor integrated circuit is transferred into the shift register, and then, the content of the shift register is outputted to an external of the semiconductor integrated circuit. However, this means also requires a number of multiplexers for the purpose of connecting all the flipflops in the form of the shift register, and therefore, the circuit scale also inevitably becomes large.
One proposal for overcoming the above mentioned problems of the prior art is disclosed in Japanese Patent Application Pre-examination Publication No. JP-A-08-170978 and its corresponding U.S. Pat. No. 5,729,553, the content of which is incorporated by reference in its entirety into this application. The above mentioned scan-path test is described even in JP-A-08-170978 and U.S. Pat. No. 5,729,553. In the scan-path test described even in JP-A-08-170978 and U.S. Pat. No. 5,729,553, an input signal serially supplied bit by bit from an external circuit is applied to the shift register, and the signals held in the shift register are supplied to a combinational circuit. Each of the flipflops constituting the shift register fetches the test result of the combinational circuit in a normal mode, and the test result fetched in the shift register is serially outputted bit by bit from the shift register to the external terminal in the scan mode. As a result, the test result can be observed.
Referring to
FIG. 4
which shows a circuit diagram of the semiconductor integrated circuit disclosed in JP-A-08-170978 and U.S. Pat. No. 5,729,553, explanation will be made, by dividing the situation into a condition in which a function inherent to a semiconductor integrated circuit
1
d
is realized while exchanging various signals between an internal circuit of the semiconductor integrated circuit and an external circuit (this will be called a “normal mode” hereinafter), and another condition in which a function test of respective circuit blocks
81
,
82
and
83
is conducted (this will be called a “test mode” hereinafter).
An input terminal
3
receives an input signal DIN supplied in a parallel format of for example 64 bits, from an external circuit when the semiconductor integrated circuit
1
d
is in the normal mode. This input signal will be called a “normal input signal” hereinafter. An output terminal
7
outputs an output signal DOUT in the parallel format of for example 64 bits, to the external circuit when the semiconductor integrated circuit
1
d
is in the normal mode. This output signal will be called a “normal output signal” hereinafter.
An input terminal
2
receives a testing input signal TIN supplied in a parallel format of for example 32 bits, from an external circuit in the test mode for the circuit block
82
. In the case that the testing signal is of 64 bits, the testing input signal is given by supplying first 32 bits at a first time, and then, remaining 32 bits at a second time.
An output terminal
8
outputs a test output signal TOUT in the parallel format of for example 32 bits, to the external circuit in the test mode for the circuit block
82
. This test output signal will be called a “test output” hereinafter.
An input terminal
6
receives a clock signal CLK from a circuit external to the semiconductor integrated circuit
1
d.
Input terminals
4
and
5
respectively receive mode control signals SEL
1
and SEL
2
for switching between the normal mode of the semiconductor integrated circuit
1
d
and the test mode of the circuit block
82
. The two mode control signals SEL
1
and SEL
2
are required in order to perform a control of multiplexers
21
and
22
and a control of multiplexers
25
and
26
, independently of each other, in the test mode of the circuit block
82
.
First, the normal mode of the semiconductor integrated circuit
1
d
will be described. The mode control signal SEL
1
is set to select output signals S
71
and S
72
of the circuit block
81
, and the mode control signal SEL
2
is set to select output signals S
76
and S
77
of the circuit block
82
. The normal input signal DIN of 64 bits given to the input terminal
3
from the external circuit is supplied to the circuit block
81
. A first 32-bit portion input of the 64-bit normal input signal thus supplied is selected as the output signal S
71
of the circuit block
81
by the multiplexer
21
, and then, supplied as a selected output signal S
73
to a flipflop
23
so that it is stored in the flipflop
23
in synchronism with the clock CLK. The first 32-bit portion input stored in the flipflop
23
is supplied as an output signal S
75
to the circuit block
82
in synchronism with the clock CLK.
The remaining second 32-bit portion input of the 64-bit normal input signal is selected as the output signal S
72
of the circuit block
81
by the multiplexer
22
, and then, supplied as a selected output signal S
74
to a flipflop
24
so that it is stored in the flipflop
24
in synchronism with the clock CLK. The second 32-bit portion input signal S
74
stored in the flipflop
24
is supplied to the circuit block
82
in synchronism with the clock CLK. An output signal S
77
of the circuit block
82
corresponding to the second 32-bit portion input signal S
74
is supplied through the multiplexer
26
to the circuit block
83
.
On the other hand, an output signal S
76
of the circuit block
82
corresponding to the first 32-bit portion input is supplied through the multiplexer
25
to the circuit block
83
. The result of the operation of the circuit block
83
is outputted to the output terminal
7
as the 64-bit output signal DOUT.
Next, the test mode of the circuit block
82

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