Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-05-17
2011-05-17
Gaffin, Jeffrey A (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S727000, C714S729000
Reexamination Certificate
active
07945829
ABSTRACT:
[PROBLEMS] To provide a semiconductor integrated circuit by which what has been referred to as two-pattern test is made possible without greatly increasing an occupying area. [MEANS FOR SOLVING PROBLEMS] The semiconductor integrated circuit is provided with a plurality of flip-flop circuits and selectors corresponding to each flip-flop circuit. Each flip-flop circuit is provided with a master latch and a slave latch connected to the master latch. The selector is electrically connected with the master latch of the flip-flop circuit to which the selector corresponds, and is also connected with the master latch of the flip-flop circuit other than the one to which the selector corresponds.
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Ito Hideo
Nanba Kazuteru
Gaffin Jeffrey A
Knobbe Martens Olson & Bear LLP
National University Corporation Chiba University
Nguyen Steve
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