Semiconductor heterostructures having reduced dislocation...

Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate

Reexamination Certificate

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C257SE21125

Reexamination Certificate

active

07829442

ABSTRACT:
Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.

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