Semiconductor heterostructure

Details Semiconductor heterostructure Semiconductor heterostructure

2007-02-08

2009-06-09

Pert, Evan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

With lattice constant mismatch

C257SE29193, C257SE21086

Reexamination Certificate

active

07544976

ABSTRACT:
A semiconductor heterostructure that includes a support substrate with a first in-plane lattice parameter, a buffer structure formed on the support substrate and having on top in a relaxed state a second in-plane lattice parameter, and a multi-layer stack of ungraded layers formed on the buffer structure. This semiconductor hetero-structure possess a lower surface roughness than other heterostructures. In the heterostructure, the ungraded layers are strained layers that comprise at least one strained smoothing layer of a semiconductor material having in a relaxed state a third in-plane lattice parameter which has a value between the first and the second lattice parameter.

REFERENCES:
patent: 6403976 (2002-06-01), Saitoh et al.
patent: 2003/0107032 (2003-06-01), Yoshida
patent: 2005/0167002 (2005-08-01), Ghyselen et al.
patent: 2006/0022200 (2006-02-01), Shiono et al.
patent: 2008/0142844 (2008-06-01), Aulnette et al.
patent: 1 020 898 (2000-07-01), None
patent: 1 566 832 (2005-08-01), None
patent: WO 2004/019391 (2004-03-01), None
G. Abstreiter, “Semiconductor Heterostructures”, 8173 Siemens Forschungs—und Entwicklungsberichte, vol. 15, No. 6, pp. 312-318 (1986).

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