Semiconductor device manufacturing: process – Making passive device – Resistor
Reexamination Certificate
2000-11-16
2002-03-19
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Making passive device
Resistor
C438S381000, C438S385000, C438S777000, C438S792000
Reexamination Certificate
active
06358808
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device with a thermally nitrided film on a high resistance film and a method of manufacturing the same.
2. Description of the Related Art
The fine patterning and high performance of a semiconductor device have still vigorously been developed. At present, a super high integration semiconductor device such as memory device and logic device has been developed to meet the design rule of 0.15 to 0.25 &mgr;m.
In conjunction with such fine patterning and high performance of the semiconductor element, a fine multilayer wiring layer is indispensable to form a semiconductor device. For this purpose, the flat and smooth surface of an interlayer insulating film between the wiring layers is strongly required. Therefore, various insulating materials have been used for the interlayer insulating film. Also, the increase of film forming speed of such an interlayer insulating film also becomes important for the reduction of manufacturing cost of the semiconductor device.
A semiconductor device with a high resistance layer, for example, an SRAM is conventionally known in which the resistance value of the high resistance layer should be precisely controlled. In the progress of manufacturing technique of the semiconductor device, the resistance value is likely to fluctuate. This is because unnecessary impurities are easily introduced from the interlayer insulating film into the high resistance layer.
As conventional techniques to solve the above problems, there are known the technique disclosed in Japanese Examined Patent Disclosure (JP-B-5-16186: hereinafter, to be referred to as a first conventional example) and the technique disclosed in Japanese Examined Patent Disclosure (JP-B-6-91189: hereinafter, to be referred to as a second conventional example).
The techniques described in the above first conventional example of a manufacturing method of the semiconductor device will now be described with reference to the drawings.
FIGS. 1A
to
1
E are cross sectional views of a semiconductor device in an order of the manufacturing process.
As shown in
FIG. 1A
, a field oxide (SiO
2
) film
102
and a gate oxide (SiO
2
) film
103
are formed in predetermined regions on a P-type single crystal Si substrate
101
. Polysilicon layers
104
and
104
a
are formed on the films
102
and
103
, respectively. A gate electrode of an MOS transistor is formed from the polysilicon layer
104
a
on the gate oxide film
103
. Subsequently, the surfaces of the polysilicon layers
104
and
104
a
are thermally oxidized and a thermal oxidation film
105
is formed. An Si
3
N
4
film
106
is formed on the thermal oxidation film
105
.
Next, as shown in
FIG. 1B
, a silicon oxide film is deposited on the whole surface of the Si
3
N
4
film
106
by a chemical vapor deposition (CVD) method, and unnecessary portions are removed by etching such that a mask insulating layer
107
is formed. Subsequently, ion implantation of phosphorus impurities or the like and heat treatment are executed to form N
+
diffusion layers
108
and
109
and an N
+
gate electrode
104
a
. The N
+
diffusion layer
108
functions as a source or drain region of the MOS transistor. In these processes, a high resistance portion
110
is formed in the polysilicon layer
104
. Also, a high density impurity is implanted into the polysilicon layer
104
a
functioning as a gate electrode.
Next, as shown in
FIG. 1C
, the Si
3
N
4
film
106
is removed such that an Si
3
N
4
film
106
a
is left under the mask insulating layer
107
.
Next, as shown in
FIG. 1D
, a PSG film
111
is deposited to cover the whole surface of the thermal oxidation film
105
, the mask insulating film
107
and the like and is smoothed. Subsequently, contact holes are formed through the insulating films laminated on the N
+
diffusion layers
108
and
109
. An Al wiring
112
which is connected to the N
+
diffusion layers
108
and
109
and another Al wiring
113
which is connected to the other N
+
diffusion layer
109
are formed, respectively.
As mentioned above, an MOS transistor is formed on the surface of the P-type Si single crystal substrate
101
and a high resistance layer composed of electrode portions of the N
+
diffusion layers
109
and the high resistance portion
110
are formed on the field oxide film
102
. The high resistance layer is used as a load resistor element.
Next, as shown in
FIG. 1E
, an interlayer insulating film
114
which covers the Al wirings
112
and
113
and the like is formed. Finally, the N
+
diffusion layers
109
function as electrode portions of the load resistor element. The surface of the high resistance portion
110
is covered by the thermally oxidized silicon film
105
and the Si
3
N
4
film
106
a.
The Si
3
N
4
film
106
a
prevents the phosphorus impurities from being diffused from the PSG film
111
into the high resistance portion
110
so that the resistance value of the high resistance layer is fluctuated.
Next, the second conventional example of the manufacturing method of a semiconductor device will now be described with reference to
FIGS. 2A
to
2
D.
FIGS. 2A
to
2
D are cross sectional views of the semiconductor device in the order of the manufacturing method.
Next, as shown in
FIG. 2A
, element isolation oxide films
202
are formed on the surface of a P-type silicon semiconductor substrate
201
. Subsequently, a gate oxide film
203
is formed. Then, a gate electrode
204
is formed of polysilicon or the like. Subsequently, N-type impurity ions such as phosphorus impurities or the like are implanted and are thermally treated, so that source and drain diffusion layers
205
are formed. At the same time, a gate electrode
204
is also formed. Thereafter, a silicon oxide film
206
is deposited to cover the whole surface.
Next, a s show n in
FIG. 2B
, a BPSG film
207
is deposited on the silicon oxide film
206
and is thermally treated, thereby the surface is flattened.
Next, as s how n in
FIG. 2C
, a first silicon nitride film
208
is formed on the BPSG film
207
. This first silicon nitride film is deposited by the CVD method to have the film thickness of 100 nm to 200 nm. A high resistance layer
209
is formed on the first silicon nitride film
208
. The high resistance layer
209
is formed of a semiconductor thin film of silicon or the like. subsequently, a second silicon nitride film
210
is deposited on the whole surface by the CVD method.
Next, as shown in
FIG. 2D
, an interlayer insulating film
211
is formed. Then, contact holes are formed through the interlayer insulating film
211
, the second silicon nitride film
210
, the first silicon nitride film
208
, BPSG film
207
, the silicon oxide film
206
, and the gate oxide film
203
by a photolithography technique and a dry etching technique. Wirings
212
are formed by filling the contact holes with conductive material.
Finally, a passivation film
213
is formed to cover the whole surface. The passivation film
213
is an insulating film such as a silicon nitride film or the like which is deposited by a plasma CVD method or the like.
According to the second embodiment, the high resistance layer
209
functions as a load resistor element of an SRAM. The high resistance layer
209
is perfectly sealed by the first silicon nitride film
208
and second silicon nitride film
210
.
The first silicon nitride film
208
and the second silicon nitride film
210
prevent the impurity ions from being diffused from the film such as a BPSG film
207
to be flattened into the high resistance portion
110
so that the resistance value of the high resistance layer
209
is fluctuated. The silicon nitride film functions as a barrier against a hydrogen ion or atom entering the high resistance layer
209
and restrains fluctuation of the resistance value of the high resistance layer.
As mentioned above, a fine multilayer wi
Jr. Carl Whitehead
Thomas Toniae M.
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