Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-11-21
2006-11-21
Crane, Sara (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S938000
Reexamination Certificate
active
07138310
ABSTRACT:
A semiconductor structure includes a strain-inducing substrate layer having a germanium concentration of at least 10 atomic %. The semiconductor structure also includes a compressively strained layer on the strain-inducing substrate layer. The compressively strained layer has a germanium concentration at least approximately 30 percentage points greater than the germanium concentration of the strain-inducing substrate layer, and has a thickness less than its critical thickness. The semiconductor structure also includes a tensilely strained layer on the compressively strained layer. The tensilely strained layer may be formed from silicon having a thickness less than its critical thickness. A method for fabricating a semiconductor structure includes providing a substrate, providing a compressively strained semiconductor on the substrate, depositing a tensilely strained semiconductor adjacent the substrate until a thickness of a first region of the tensilely strained semiconductor is greater than a thickness of a second region of the tensilely strained semiconductor, forming a n-channel device on the first region, and forming a p-channel device on the second region.
REFERENCES:
patent: 4497683 (1985-02-01), Celler et al.
patent: 4710788 (1987-12-01), Dämbkes et al.
patent: 4920076 (1990-04-01), Holland et al.
patent: 4990979 (1991-02-01), Otto
patent: 5155571 (1992-10-01), Wang et al.
patent: 5241197 (1993-08-01), Murakami et al.
patent: 5291439 (1994-03-01), Kauffmann et al.
patent: 5312766 (1994-05-01), Aronowitz et al.
patent: 5327375 (1994-07-01), Harari
patent: 5442205 (1995-08-01), Brasen et al.
patent: 5461243 (1995-10-01), Ek et al.
patent: 5479033 (1995-12-01), Baca et al.
patent: 5523592 (1996-06-01), Nakagawa et al.
patent: 5534713 (1996-07-01), Ismail et al.
patent: 5596527 (1997-01-01), Tomioka et al.
patent: 5617351 (1997-04-01), Bertin et al.
patent: 5683934 (1997-11-01), Candelaria
patent: 5739567 (1998-04-01), Wong
patent: 5777347 (1998-07-01), Bartelink
patent: 5780922 (1998-07-01), Mishra et al.
patent: 5786612 (1998-07-01), Otani et al.
patent: 5792679 (1998-08-01), Nakato
patent: 5808344 (1998-09-01), Ismail et al.
patent: 5847419 (1998-12-01), Imai et al.
patent: 5891769 (1999-04-01), Liaw et al.
patent: 5906951 (1999-05-01), Chu et al.
patent: 5951757 (1999-09-01), Dubbelday et al.
patent: 5963817 (1999-10-01), Chu et al.
patent: 5986287 (1999-11-01), Eberl et al.
patent: 5998807 (1999-12-01), Lustig et al.
patent: 6013134 (2000-01-01), Chu et al.
patent: 6058044 (2000-05-01), Sugiura et al.
patent: 6059895 (2000-05-01), Chu et al.
patent: 6096590 (2000-08-01), Chan et al.
patent: 6107653 (2000-08-01), Fitzgerald
patent: 6111267 (2000-08-01), Fischer et al.
patent: 6117750 (2000-09-01), Bensahel et al.
patent: 6130453 (2000-10-01), Mei et al.
patent: 6143636 (2000-11-01), Forbes et al.
patent: 6204529 (2001-03-01), Lung et al.
patent: 6207977 (2001-03-01), Augusto
patent: 6249022 (2001-06-01), Lin et al.
patent: 6251755 (2001-06-01), Furukawa et al.
patent: 6266278 (2001-07-01), Harari et al.
patent: 6339232 (2002-01-01), Takagi
patent: 6350993 (2002-02-01), Chu et al.
patent: 6399970 (2002-06-01), Kubo et al.
patent: 6407406 (2002-06-01), Tezuka
patent: 6461945 (2002-10-01), Yu
patent: 6498359 (2002-12-01), Schmidt et al.
patent: 6555839 (2003-04-01), Fitzgerald
patent: 6583437 (2003-06-01), Mizuno et al.
patent: 6593191 (2003-07-01), Fitzgerald
patent: 6593641 (2003-07-01), Fitzgerald
patent: 6600170 (2003-07-01), Xiang
patent: 6646322 (2003-11-01), Fitzgerald
patent: 6649480 (2003-11-01), Fitzgerald et al.
patent: 6677192 (2004-01-01), Fitzgerald
patent: 6703688 (2004-03-01), Fitzgerald
patent: 6723661 (2004-04-01), Fitzgerald
patent: 6730551 (2004-05-01), Lee et al.
patent: 2001/0003364 (2001-06-01), Sugawara et al.
patent: 2002/0100942 (2002-08-01), Fitzgerald et al.
patent: 2002/0123197 (2002-09-01), Fitzgerald et al.
patent: 2002/0125471 (2002-09-01), Fitzgerald et al.
patent: 2002/0125497 (2002-09-01), Fitzgerald
patent: 2002/0140031 (2002-10-01), Rim
patent: 2002/0197803 (2002-12-01), Leitz et al.
patent: 2003/0013323 (2003-01-01), Hammond et al.
patent: 2003/0052334 (2003-03-01), Lee et al.
patent: 2003/0057439 (2003-03-01), Fitzgerald
patent: 2003/0077867 (2003-04-01), Fitzgerald
patent: 2003/0089901 (2003-05-01), Fitzgerald
patent: 2003/0227013 (2003-12-01), Currie et al.
patent: 2004/0026765 (2004-02-01), Currie et al.
patent: 41 01 167 (1992-07-01), None
patent: 0 683 522 (1995-11-01), None
patent: 0 828 296 (1998-03-01), None
patent: 0 829 908 (1998-03-01), None
patent: 0 838 858 (1998-04-01), None
patent: 0 844 651 (1998-05-01), None
patent: 1 020 900 (2000-07-01), None
patent: 1 174 928 (2002-01-01), None
patent: 63122176 (1988-05-01), None
patent: 4-307974 (1992-10-01), None
patent: 7-106446 (1995-04-01), None
patent: 9-219524 (1997-08-01), None
patent: 11-233744 (1999-08-01), None
patent: 2000-21783 (2000-01-01), None
patent: 2001-160594 (2001-06-01), None
patent: 2001-168342 (2001-06-01), None
patent: 2001-319935 (2001-11-01), None
patent: 02241195 (2002-08-01), None
patent: 98/59365 (1998-12-01), None
patent: 99/53539 (1999-10-01), None
patent: 00/54338 (2000-09-01), None
patent: 01/54202 (2001-07-01), None
patent: 01/93338 (2001-12-01), None
patent: 01/99169 (2001-12-01), None
patent: 02/13262 (2002-02-01), None
patent: 02/15244 (2002-02-01), None
patent: 02/47168 (2002-06-01), None
patent: 02/071488 (2002-09-01), None
patent: 02/071491 (2002-09-01), None
patent: 02/071495 (2002-09-01), None
Communication Relating to the Results of the Partial International Search for PCT/US03/18123, Dec. 17, 2003, 6 pages.
Leitz et al., “Channel Engineering of SiGe-Based Heterostructures for High Mobility MOSFETs,”Materials Research Society Symposium Proceedings, vol. 686 (2002), pp. 113-118.
Leitz et al., “Hole mobility enhancements in strained Si/Si1-yGeyp-type metal-oxide-semiconductor field-effect transistors grown on relaxed Si1-xGex(x<y) virtual substrates,”Applied Physics Letters, vol. 79, No. 25 (Dec. 17, 2001), pp. 4246-4248.
Liu et al., “A Novel Sidewall Strained-Si Channel nMOSFET,”IEDM, (1999), pp. 63-66.
“2 Bit/Cell EEPROM Cell Using Band-to-Band Tunneling for Data Read-Out,”IBM Technical Disclosure Bulletin, vol. 35, No. 4B (Sep. 1992) pp. 136-140.
Aigouy et al., “MOVPE Growth and optical characterization of ZnSe/ZnS strained layer superlattices,”Superlattices and Microstructures, vol. 16, No. 1 (1994) pp. 71-76.
Anonymous, “Germanium P-Channel Mosfet,”IBM Technical Disclosure Bulletin, vol. 28, No. 2 (Jul. 1, 1985) p. 500.
Armstrong et al., “Design of Si/SiGe Heterojunction Complementary Metal-Oxide-Semiconductor Transistors,”IEDM Technical Digest(1995) pp. 761-764.
Armstrong, “Technology for SiGe Heterostructure-Based CMOS Devices,” Submitted to the Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science on Jun. 30, 1999, pp. 1-154.
Barradas et al., “RBS analysis of MBE-grown Si/Ge/(001) Si heterostructures with thin, high Ge content SiGe channels for HMOS transistors,”Modern Physics Letters B(2001) (abstract).
Bouillon et al., “Search for the optimal channel architecture for 0.18/0.12 μm bulk CMOS Experimental study,”IEEE, (1996) pp. 21.2.1-21.2.4.
Bufler et al., “Hole transport in strained Si1-xGexalloys on Si1-yGeysubstrates,”Journal of Applied Physics, vol. 84, No. 10 (Nov. 15, 1998) pp. 5597-5602.
Canaperi et al., “Preparation of a relaxed Si-Ge layer on an insulator in fabricating high-speed semiconductor devices with strained epitaxial films,”Intern. Business Machines Corporation, USA (2002) (abstract).
Carlin et al., “High Efficiency GaAs-on-Si Solar Cells with High VocUsing Graded GeSi Buffers,”IEEE(2000) pp. 1006-1011.
Cheng et al., “Electron Mobility Enhancement in Strained-Si n-MOSFETs Fabricated on SiGe-on-Insulator (SGOI) Substrates,”IEEE Electron Device Letters, vol. 22, No
Currie Matthew T.
Fitzgerald Eugene A.
Leitz Christopher W.
Lochtefeld Anthony J.
AmberWave Systems Corporation
Crane Sara
Goodwin & Procter LLP
LandOfFree
Semiconductor devices having strained dual channel layers does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor devices having strained dual channel layers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor devices having strained dual channel layers will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3666676