Semiconductor devices having dual capping layer patterns and...

Details Semiconductor devices having dual capping layer patterns and... Semiconductor devices having dual capping layer patterns and...

2006-07-25

2006-07-25

Quach, T. N. (Department: 2826)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S279000, C438S586000, C438S637000, C257SE21645

Reexamination Certificate

active

07081389

ABSTRACT:
Some embodiments provide a semiconductor substrate having a cell array region and a peripheral circuit region. A plurality of word line patterns are placed in the cell array region, each of which include a word line and a word line capping layer pattern stacked thereon. At least one gate pattern including a gate electrode and a gate capping layer pattern is formed in the peripheral circuit region, the gate capping layer pattern and the word line capping layer pattern having different etching selectivity ratios. A pad interlayer insulating layer and a bit line interlayer insulating layer having approximately the same etching selectivity ratio as the gate capping layer pattern are sequentially formed over a surface of the semiconductor substrate having the gate spacers.

REFERENCES:
patent: 6127260 (2000-10-01), Huang
patent: 6242809 (2001-06-01), Lee
patent: 6309960 (2001-10-01), Sukekawa
patent: 6326270 (2001-12-01), Lee et al.
patent: 6387759 (2002-05-01), Park et al.
patent: 6423627 (2002-07-01), Carter et al.
patent: 6451708 (2002-09-01), Ha
patent: 6482699 (2002-11-01), Hu et al.

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