Semiconductor devices having DRAM cells and methods of...

Details Semiconductor devices having DRAM cells and methods of... Semiconductor devices having DRAM cells and methods of...

2007-07-24

2007-07-24

Lee, Calvin (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S239000

Reexamination Certificate

active

11252963

ABSTRACT:
A semiconductor device comprises bit line landing pads and storage landing pads disposed on both sides of the bit line landing pads overlying a substrate. A bit line interlayer insulating layer overlies the bit line and storage landing pads. A plurality of bit line patterns are disposed on the bit line interlayer insulating layer. The bit line patterns each include a bit line and a bit line capping layer pattern. Line insulating layer patterns are placed on a top surface of the bit line interlayer insulating layer. Upper contact holes are placed in a region between the bit line patterns and higher than upper surfaces of the bit lines. Contact hole spacers cover the side walls of the upper contact holes. Lower contact holes are self-aligned with the upper contact holes and extend through the line insulating layer patterns and the bit line interlayer insulating layer, thereby exposing the storage node landing pads.

REFERENCES:
patent: 6136643 (2000-10-01), Jeng et al.
patent: 2004/0266101 (2004-12-01), Park et al.
patent: 2001-0005108 (2001-01-01), None
patent: 2002-0088980 (2002-11-01), None
English language abstract of Korea Publication No. 2001-0005108.
English language abstract of Korea Publication No. 2002-0088980.

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