Semiconductor devices and their manufacture

Details Semiconductor devices and their manufacture Semiconductor devices and their manufacture

2002-08-26

2004-08-24

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S296000, C438S424000

Reexamination Certificate

active

06780714

ABSTRACT:

This invention relates to semiconductor devices and their manufacture, and particularly in areas where an electrically conductive connection extends over an edge region of an active area of the device. The invention relates particularly, but not exclusively, to the formation of a gate connection at the perimeter of a MOSFET (i.e. an insulated-gate field-effect transistor) such as, for example, a trench-gate power MOSFET.
Trench-gate power MOSFETs are well-known semiconductor devices having active device cells comprising an insulated gate trench that accommodates the trench-gate and extends from a source region through a channel-accommodating region and into an underlying drain region of the MOSFET. The trench-gate is dielectrically coupled to the channel-accommodating region by an intermediate gate-dielectric layer (typically oxide) at sidewalls of the gate trench.
Particular examples of a trench-gate power MOSFET are disclosed in published European patent application EP-A-1 009 035, which is concerned with improving the breakdown characteristics of the device, particularly in device termination areas. Thus, measures are taken to relieve the electric field at the upper and bottom end edges (UE & BE respectively) of the gate trench, where a gate connection extends to a gate pad and/or field-plate beyond the active cellular area of the device. The whole contents of EP-A-1 009 035 are hereby incorporated herein as reference material.
At the perimeter area around the active area, the channel-accommodating region and the gate trench network terminate in an edge region of the first conductivity type. This termination enhances the breakdown voltage at the bottom end edge (BE) of the gate trench. The edge region may be an extension of the channel-accommodating region, or it may be a deeper and more highly doped region than the channel-accommodating region. In each case, the gate trench is provided after providing the edge region and the channel-accommodating region. The gate connection is then provided over this edge region.
EP-A-1 009 035 discloses various gate connection schemes for relieving and/or eliminating the electric field in insulating films at the upper end edge (UE) of the gate trench. In particular, the gate connection is kept away from this upper end edge (UE) of the gate trench. The present Applicants note that, in some of these embodiments (FIGS. 46, 57, 61 & 67 of EP-A-1 009 035), the resulting gate connection comprises electrically parallel conductive fingers as a consequence of the provision of these spaces around parallel trench-gate ends.
The present invention is based on a different approach, in respect of which the present
FIG. 1
shows an experimental trench-gate MOS transistor structure, not previously published. The drawing is a simplified MOST schematic, e.g. its source region
13
and source electrode
23
are omitted. In this case, the insulated trench-gate
11
,
16
is formed before the so-called “P-body implant” that provides the p-type channel-accommodating region
15
for this n-channel device. This sequence is found advantageous in optimising the channel profile in a trench-gate MOSFET.
Thus, in order to optimise the channel profile, the formation of the gate dielectric
16
(typically by oxidation) is preferably done before the P-body implant. This gives a larger degree of freedom in the thermal budget used to form the channel-accommodating region
15
(P-body), resulting in a lower channel resistance. However, the P-body implant (and any deeper P implant) cannot be performed directly after forming the gate oxide
16
, because this would result in implanting the dopant at the bottom of the gate trench
20
, which is undesirable. Therefore, the implants are carried out after depositing and patterning the gate
11
. Furthermore, performing the P-body implant (and any deeper P implant) after forming the trench-gate
11
is preferable in order to reduce outdiffusion of the P-dopant during sacrificial oxide and gate oxide growth in the trench
20
.
However, this sequence of performing the implants after forming the insulated trench-gate
11
,
16
results in an absence of these implants at the edge of the MOSFET, as shown in FIG.
1
. Thus, it prevents inclusion of the P-body (or deeper P-region) below a gate connection
110
to, for example, a gate bond pad
114
and/or field-plate
114
at the edge termination of the active device area
120
. This absence of the P-body (or deeper P-region) can cause premature voltage breakdown and loss of ruggedness.
Thus,
FIG. 1
shows the resulting end RE of the P-body
15
at the perimeter of the active area
120
of the trench-gate MOS transistor. It can be seen that this end RE does not extend as far as the outer trenches
12
at the device perimeter in FIG.
1
. Consequently, a high electric field is experienced at the base of these perimeter trenches
12
having no P-body
15
. This leads to premature breakdown, as shown by the star BD in FIG.
1
.
It is an object of the present invention to address the above-mentioned disadvantages in semiconductor devices generally, as well as in MOSFETs. Furthermore, it is an object of an important embodiment of the present invention to provide a trench-gate MOSFET having better breakdown voltage characteristics.
According to a first aspect of the present invention there is provided a method of manufacturing a semiconductor device comprising an electrically conductive connection that extends over an edge region of an active area of the device,
wherein the connection comprises electrically-parallel conductive fingers, and wherein the method includes the steps of:
(a) forming the fingers over an area where the edge region is to be provided;
(b) subsequently implanting dopant of a first conductivity type for the edge region via spaces between said fingers; and
(c) diffusing the said dopant beneath the fingers so as to form the edge region as an at least substantially continuous region of the first conductivity type that extends beneath the fingers and beneath the spaces between the fingers.
This use of connection fingers and their associated spaces advantageously allows the edge region to be provided after formation of the connection (and hence after trench-gate formation in trench-gate device manufacture), by diffusion of its dopant beneath the fingers.
The present invention can be used advantageously to provide an edge region (such as a termination extension of the channel-accommodating region and/or a guard-ring and/or ruggedness region) below a gate connection of a MOSFET device. It can be used very advantageously in a trench-gate cellular power MOSFET. Specific trench-gate features are set out in claim
3
to
7
,
13
and
14
. However, the present invention may be used advantageously to provide connections over edge regions in other types of semiconductor device, for example in a bipolar transistor or even in an integrated circuit.
Wide ranges of values for the particular parameters of the fingers and of the dopant diffusion are possible, depending on the particular device area where the invention is used, on device-feature dimensions, and on the specific manufacturing technology used.
The dopant diffusion step (c) maybe carried out in one or more stages, after the doping step (b) and/or during the doping step (b). The diffusion may take place over a time period of between, for example, 5 minutes and 200 minutes, and typically between about 10 minutes and 100 minutes. The diffusion may be performed at temperatures in excess of approximately 950° C., and preferably above approximately 1,050° C. Typically, the dopant for a P-type region may be boron.
The fingers (defined in step (a)) may have a width in the range of, for example, 0.1 to 20 &mgr;m, and typically in the range approximately 0.6 to 2 &mgr;m. The fingers may be substantially parallel to one another, to form a connection of compact width. The gaps (spaces) between adjacent fingers may be between 1 and 50 &mgr;m, for example, 2 to 17 &mgr;m. The width of these spaces is preferably approximately 3 times a finger w

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