Semiconductor devices and methods of manufacturing the same

Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Multiple layers

Reexamination Certificate

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C438S786000, C257SE21267, C257S637000

Reexamination Certificate

active

07569495

ABSTRACT:
Semiconductor devices and methods of manufacturing the same are disclosed. In a disclosed method, a dangling bond in the active region(s) is removed by providing an enough H2in the PMD liner layer and the interlayer insulating layer directly contacting the active regions, and then gradually diffusing the H2in a subsequent heat treatment. The method includes forming a gate electrode having a side wall spacer, forming source and drain regions, forming a PMD liner layer by sequentially forming a SiO2:H layer, a SiON:H layer and a SiN:H layer above the gate electrode and the source and drain regions, forming an interlayer insulating layer above the PMD liner layer, and diffusing hydrogen in the PMD liner layer and the interlayer insulating layer to the source and drain region by N2annealing or Ar annealing.

REFERENCES:
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patent: 6287951 (2001-09-01), Lucas et al.
patent: 6372569 (2002-04-01), Lee et al.
patent: 2002/0192885 (2002-12-01), Miyasaka
patent: 2004/0121571 (2004-06-01), Uchikoshi et al.
Schulze, Hans-Joachim et al., Passivation Layer for Power Semiconductors with PN junctions appearing on the surface, Jul. 17, 1998, PCT/DE99/01924.

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