Semiconductor devices and methods of fabricating the same

Details Semiconductor devices and methods of fabricating the same Semiconductor devices and methods of fabricating the same

2002-11-06

2004-05-04

Eckert, George (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S372000, C257S369000, C257S374000, C257S503000, C257S508000

Reexamination Certificate

active

06730971

ABSTRACT:

RELATED APPLICATION
This application claims priority and benefit of Korean Patent Application No. 2001-80481, filed on Dec. 18, 2001, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
The present disclosure relates to semiconductor devices and, more particularly, to MOS transistors and their methods of fabrication with well or substrate body bias provisions electrically connected to one of a transistor's source/drain regions.
A semiconductor integrated circuit may comprise a plurality of NMOS transistors on P-type well(s) and PMOS transistor on N-type well(s). Generally, the semiconductor integrated circuit may comprise provisions for grounding or applying a voltage to the N-type well(s) or the P-type well(s). For conventional devices, the transistors are formed on active regions of the wells, which may extend to regions separate and beyond the fabricated transistors to receive well or substrate body biasing. For some conventional devices, a plurality of transistors may be formed on a single well, which likewise may receive well biasing at region(s) separate from the plurality of transistors.
Referring to
FIG. 1
, a conventional semiconductor device may comprise device isolation layer
12
disposed in a predetermined region of a semiconductor substrate. The device isolation layer
12
may comprise an outline that defines first and second active regions in respective N-type and P-type regions
10
a
,
10
b
of the substrate. A PMOS transistor may be formed on the first active region of N-type region
10
a
between sidewalls
13
A of isolation layer
12
. Likewise, an NMOS transistor may be formed on the second active region of the P-type region
10
b
between sidewalls
13
B of isolation layer
12
.
The PMOS transistor may comprise first gate pattern
14
a
crossing the first active region. P-type source/drain regions
16
a
of the PMOS transistor may be formed in the first active region on opposite sides of first gate pattern
14
a
. The NMOS transistor may comprise second gate pattern
14
b
crossing the second active region. N-type source/drain regions
16
b
of the NMOS transistor may be formed in the second active region on opposite sides of the second gate pattern
14
b.
As shown in
FIG. 1
, such conventional semiconductor device may further comprise well bias regions
18
a
and
18
B for enabling connection of respective N-well and P-well regions to receive respective well or substrate body biasings. Well bias regions
18
a
and
18
b
may be formed separate from their respective transistors but within the active regions of the transistors.
For highly integrated semiconductor devices, well bias regions may be formed at regular intervals in predetermined regions of the semiconductor substrate for a plurality of transistors and active regions. Referencing
FIG. 2
, such conventional semiconductor device
21
may comprise well bias regions
28
coupled at regular intervals to bias well
20
B of the semiconductor substrate.
For this example, further referencing the conventional device of
FIG. 2
, device isolation layer
22
may be formed in a predetermined region of the semiconductor substrate
20
and with sidewalls
23
forming an outline to define a plurality of active regions. Transistors may be formed on the respective active regions. Each well bias region
28
which may be associated with a group of the plurality of the transistors may be coupled to a common well bias region
28
. Unfortunately, however, the single common well bias region
28
of such conventional device as shown in
FIG. 2
may adversely affect an integrity of transistors
25
that may be more distant well bias region
28
. Such distant transistors may be more vulnerable to latch-up phenomenon or abnormal noise.
SUMMARY OF THE INVENTION
In accordance with an embodiment of the present invention, highly integrated semiconductor devices may be fabricated with structures resistant to latch-up phenomenon.
In one exemplary embodiment of the present invention, a semiconductor device comprises a substrate of first conductivity type. A device isolation layer may be disposed in a predetermined region of the substrate and may comprise an outline to define an active region. Second conductivity type impurities may be diffused into an impurity diffused layer within the active region. A silicide layer may be formed to cover the impurity diffused layer of second conductivity type. A recess in the device isolation layer may expose a region of the substrate of first conductivity type adjacent to the impurity diffused layer of second conductivity type. The silicide layer may be formed to cover the impurity diffused layer of second conductivity type. The silicide layer may also extend into the recess to cover a region of the substrate of first conductivity type that is exposed by the recess.
In a further embodiment of the present invention, the active region may include source/drain regions of a transistor. A gate pattern for the transistor may cross the active region with the source/drain regions of second conductivity type on opposite sides of the gate pattern. Each one of the source/drain regions of second conductivity type may be covered with the salicide layer. A recess of a device isolation layer may expose a predetermined region of the semiconductor substrate of first conductivity type that is adjacent to one of the source/drain regions of second conductivity type. The salicide layer that covers the one source/drain region may extend into the recess to cover the surface of the substrate of first conductivity type that faces inwardly toward the recess.
In another embodiment of the present invention, a semiconductor device comprises a semiconductor substrate of N-type and P-type regions. A device isolation layer may be formed in predetermined regions of the semiconductor substrate with an outline to define first and second active regions in the respective N-type and P-type regions of the substrate. First and second gate patterns may cross the first and second active regions, respectively. A pair of P-type source/drain regions may be formed in the first active region at opposite sides of the first gate pattern. A pair of N-type source/drain regions may be formed in the second active region at opposite sides of the second gate pattern. A suicide layer may cover N-type source/drain regions and the P-type source/drain regions. The device isolation layer may further comprise a first recess that exposes a portion of the N-type region of the substrate adjacent to one of the P-type source/drain regions. The device isolation layer may also comprise a second recess that exposes a portion of the P-type region of the substrate adjacent to one of the N-type source/drain regions. The salicide layer on the select one of the N-type source/drain regions may extend into the first recess to cover the face of the P-type region of the substrate that faces the first recess. Likewise, the salicide layer on the selected one of the P-type source/drain regions may extend into the second recess to cover the face of the N-type region of the substrate that faces the second recess.
In accordance with another embodiment of the present invention, a method of fabricating a semiconductor device comprises forming a device isolation layer in a predetermined region of a substrate of first conductivity type. The isolation layer may be formed with an outline to define an active region. Impurities of second conductivity type may be formed in a impurity diffusion region of the active region. A predetermined region of the device isolation layer may then be etched to form a recess and expose a portion of the substrate of first conductivity type adjacent to the impurity diffusion region of second conductivity type. A suicide layer may then be formed to cover the impurity diffused region of second conductivity type and to cover the exposed regions of the substrate of first conductivity type within the recess.
In a further embodiment of the present invention, a gate pattern may be formed to cross

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