Semiconductor devices and methods for same

Details Semiconductor devices and methods for same Semiconductor devices and methods for same

2000-03-03

2002-09-03

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S795000, C438S910000

Reexamination Certificate

active

06444533

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention resides in the field of semiconductor devices, and in particular relates to methods for treating semiconductor devices or components thereof in order to reduce the degradation of semiconductor device characteristics over time.
As further background, hydrogen passivation has become a well-known and established practice in the fabrication of semiconductor devices. In the hydrogen passivation process, defects which affect the operation of semiconductor devices are removed. For example, such defects have been described as recombination/generation centers on active components of semiconductor devices. These centers are thought to be caused by dangling bonds which introduce states in the energy gap which remove charged carriers or add unwanted charge carriers in the device, depending in part on the applied bias. While dangling bonds occur primarily at surfaces or interfaces in the device, they also are thought to occur at vacancies, micropores, dislocations, and also to be associated with impurities.
Over the years a number of hydrogen passivation processes have been proposed. For example, U.S. Pat. No. 3,923,559 describes a process in which, in the fabrication of a device such as a metal oxide semiconductor field effect transistor (MOSFET) device, hydrogen gas is introduced into the layer of silicon dioxide prior to deposition of the metal electrodes. Thereafter, the metal electrodes are deposited, thereby trapping the hydrogen gas within the device. Thereafter, the device is annealed at an elevated temperature and the hydrogen previously introduced migrates to the silicon surface to neutralize undesirable interface states produced during device fabrication.
U.S. Pat. No. 4,151,007 describes a passivation process in which the last fabrication step in the device fabrication involves heating the device in an ambient of hydrogen gas at a temperature of 650° C. to 950° C. This final hydrogen anneal step reportedly negated the effects of slow trapping and thus improved the stability of the MOS structures.
U.S. Pat. No. 4,113,514 describes a passivation process which involves exposing the device to atomic hydrogen, for example generated using a glow-discharge apparatus acting upon molecular hydrogen, at a temperature lower than 450° C. Somewhat similarly, U.S. Pat. No. 4,331,486 describes a passivation process in which a hydrogen plasma is created to treat the semiconductor devices with atomic hydrogen.
U.S. Pat. No. 3,849,204 describes a passivation process which involves implanting hydrogen ions in the area of defects, and thereafter annealing the substrate in an inert atmosphere to eliminate the interface states.
Another problem which has arisen in the semiconductor industry is the degradation of device performance by hot carrier effects. This is particularly of concern with respect to smaller devices in which proportionally larger voltages are used. When such high voltages are used, channel carriers can be sufficiently energetic to enter an insulating layer and degrade device behavior. For example, in silicon-based P-channel MOSFETs, channel strength can be reduced by trapped energetic holes in the oxide which lead to a positive oxide charge near the drain. On the other hand, in N-channel MOSFETs, gate-to-drain shorts may be caused by electrons entering the oxide and creating interface traps and oxide wear-out. “Drain engineering” has been an emerging field attempting to cope with these problems, for example involving the use of a lightly-doped drain (LDD) in which a lightly-doped extension of the drain is created between the channel and the drain proper. For additional detail as to these and other potential measures for reducing susceptibility to hot carrier effects, reference can be made for example to U.S. Pat. Nos. 5,352,914, 5,229,311, 5,177,571, 5,098,866, 4,859,620, 4,691,433 and 4,521,698. Such solutions are, however, expensive because they typically complicate the fabrication process. Their avoidance, or at least their simplification, would be desirable.
In light of this background there exists a need for improved passivation processes and devices resulting from such processes. The present invention addresses these needs.
SUMMARY OF THE INVENTION
It has been discovered that semiconductor devices, for example including MOS devices, can be advantageously treated with deuterium to improve their operational characteristics. Accordingly, one preferred embodiment of the present invention provides a method for treating a semiconductor device which includes a step of passivating the device with deuterium. Semiconductor devices so passivated also form a part of the present invention.
In a more preferred aspect, the invention provides a semiconductor device which includes a semiconductor layer including a Group III, IV or V element, or a mixture thereof. The device also includes an insulative (dielectric) layer atop the semiconductor layer, wherein deuterium atoms are covalently bound to atoms of the Group III, IV or V element in amounts sufficient to significantly increase resilience of the device to hot carrier effects.
Additional embodiments of the invention provide processes in which deuterium-treated semiconductor devices of the invention are operated under conditions which produce hot carrier effects, and in which deuterium is introduced into the semiconductor device after fabrication is complete, and/or in one or more of a variety of fabrication steps, and the introduced deuterium is used to improve the operative characteristics of the device.
Methods and devices of the invention provide unique advantages in the field of semiconductors, their preparation and their use. For example, the provided device demonstrate improved operational characteristics and resist aging or “depassivation” due to hot-carrier effects. Moreover, devices of the invention can be operated using higher voltages to increase performance, while better resisting degradation due to hot-carrier effects. Likewise, methods of the invention are beneficial for preparing radiation hard devices, which are usually operated at higher voltages. Further, methods of the invention can be readily and economically practiced and incorporated into existing fabrication techniques, and may eliminate the need for costly and/or complicated measures otherwise taken to guard against hot electron effects, for example lightly doped drain (LDD) technology, or provide more processing flexibility in the conduct of such measure.
Additional objects, features and advantages of the invention will be apparent from the following description.


REFERENCES:
patent: 3849204 (1974-11-01), Fowler
patent: 3923559 (1975-12-01), Sinha
patent: 4027380 (1977-06-01), Deal et al.
patent: 4113514 (1978-09-01), Pankove et al.
patent: 4151007 (1979-04-01), Levinstein et al.
patent: 4290825 (1981-09-01), Dearnaley et al.
patent: 4331486 (1982-05-01), Chenevas-Paule et al.
patent: 4620211 (1986-10-01), Baliga et al.
patent: 4992840 (1991-02-01), Haddad et al.
patent: 5059551 (1991-10-01), Chevallier et al.
patent: 5162892 (1992-11-01), Hayashi et al.
patent: 5179029 (1993-01-01), Gottscho et al.
patent: 5248348 (1993-09-01), Miyachi et al.
patent: 5250446 (1993-10-01), Osawa et al.
patent: 5264724 (1993-11-01), Brown et al.
patent: 5320975 (1994-06-01), Cederbaum et al.
patent: 5504020 (1996-04-01), Aomori et al.
patent: 5514628 (1996-05-01), Enomoto et al.
patent: 5571339 (1996-11-01), Ringel et al.
patent: 5693961 (1997-12-01), Hamada
patent: 5872387 (1999-02-01), Lyding et al.
patent: 5972765 (1999-10-01), Clark et al.
patent: 6027990 (2000-02-01), Thakur et al.
patent: WO-9419829 (1994-09-01), None
Kizilyalli et al., “Deuterium Post-Metal Annealing of MOSFET's for Improved Hot Carrier Mobility”, IEEE Electron Device Letters, vol. 18,. No. 3, Mar. 1997, pp. 81-83.*
Wolf, “Silicon Processing for the VLSI Era vol. 2: Process Integration”, p. 328, 1990, Lattice Press.*
Avouris et al., “STM-Induced H Atom Desorption From Si(100): Isotope Effects And Site Selectivity”, Chemical Physics Letters, vol. 257, pp

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