Semiconductor devices and methods for manufacturing the same

Details Semiconductor devices and methods for manufacturing the same Semiconductor devices and methods for manufacturing the same

2001-01-13

2004-08-31

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S255000, C438S381000

Reexamination Certificate

active

06784047

ABSTRACT:

TECHNICAL FIELD
The present invention relates to semiconductor devices that mix-mount DRAMs (Dynamic Random Access Memories) and other device elements in the same chip, and methods for manufacturing the same.
BACKGROUND
In recent years, mixed-mounting of various types of circuits is required in consideration of various factors, such as, for example, to shorten the chip interface delay, to reduce the cost per board area, and to reduce the cost in design and development of boards. There are problems in the mix-mounting technology in that the process becomes complex and the IC cost increases.
SUMMARY
One embodiment relates to a method for manufacturing a semiconductor device, the semiconductor device having a DRAM including a cell capacitor formed in a DRAM region of a semiconductor substrate, and a capacitor element formed in an analog element region of the semiconductor substrate. The method includes (a) simultaneously forming a bit line that is a component of the DRAM and a connection layer that is located in a common layer with the bit line and this is used to electrically connect a lower electrode of the capacitor element and another semiconductor element; (b) simultaneously forming a storage node of the cell capacitor and the lower electrode; (c) simultaneously forming a dielectric layer of the cell capacitor and a dielectric layer of the capacitor element; and (d) simultaneously forming a cell plate of the cell capacitor and an upper electrode of the capacitor element.
Embodiments also includes a semiconductor device having a DRAM including a cell capacitor formed in a DRAM region of a semiconductor substrate, and a capacitor element formed in an analog element region of the semiconductor substrate. The semiconductor device includes an interlayer dielectric layer, an embedded connection layer and a connection layer, wherein the interlayer dielectric layer is located between the semiconductor substrate and the capacitor element. The connection layer and the embedded connection layer are used to electrically connect a lower electrode of the capacitor element to another semiconductor element. The connection layer is located in a common layer of a bit line that is a component of the DRAM. The embedded connection layer is located in a connection hole formed in the interlayer dielectric layer. One end of the embedded connection layer connects to the lower electrode at a bottom surface of the lower electrode, and another end of the embedded connection layer connects to the connection layer.
Embodiments also relate to a method for manufacturing a semiconductor device, the semiconductor device having a DRAM including a cell capacitor formed in a DRAM region of a semiconductor substrate, and a capacitor element formed in an analog element region of the semiconductor substrate. The method includes forming a first conducting layer and etching a portion of the first conducting layer to form a bit line that is a component of the DRAM and a connection layer that is located in a common layer with the bit line and used to electrically connect a lower electrode of the capacitor element and another semiconductor element. The method also includes forming a second conducting layer and etching a portion of the second conducting layer to form a storage node of the cell capacitor and the lower electrode. The method also includes forming a dielectric layer and etching a portion of the dielectric layer to form a dielectric layer of the cell capacitor and a dielectric layer of the capacitor element. In addition, the method includes forming a third conducting layer and etching a portion of the third conducting layer to form a cell plate of the cell capacitor and an upper electrode of the capacitor element.


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