Semiconductor devices and methods for manufacturing the same

Details Semiconductor devices and methods for manufacturing the same Semiconductor devices and methods for manufacturing the same

2001-05-01

2004-11-23

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S299000, C438S301000, C438S302000

Reexamination Certificate

active

06821858

ABSTRACT:

Applicants hereby incorporate by reference Japanese Application No. 2000-132339, filed May 1, 2000 in its entirety. Applicants hereby incorporate by reference U.S. application Ser. No. 09/847,071 in its entirety.
1. Technical Field
The present invention relates to semiconductor devices and methods for manufacturing the same, including semiconductor devices having an improved dielectric strength and methods for manufacturing the same.
2. Related Art
Presently, there is known a field effect transistor having a LOCOS (Local Oxidation Of Silicon) offset structure, which is a field effect transistor having an improved dielectric strength. A field effect transistor having a LOCOS offset structure is a transistor in which a LOCOS layer is provided between a gate dielectric layer and a drain region, wherein an offset impurity layer is formed below the LOCOS layer. For example, Japanese patent No. 2705106 and Japanese patent No. 2534508 describe field effect transistors having LOCOS offset structure.
It is noted that a field effect transistor having a LOCOS offset structure has a problem in which a bird's beak is formed at an end of the LOCOS such that the active region is narrowed.
SUMMARY
One embodiment relates to a semiconductor device including a field effect transistor, the field effect transistor including a gate dielectric layer, a source region and a drain region. A first semi-recessed LOCOS layer is provided between the gate dielectric layer and the drain region, and a second semi-recessed LOCOS layer is provided between the gate dielectric layer and the source region. A first offset impurity layer is provided below the first semi-recessed LOCOS layer, and a second offset impurity layer is provided below the second semi-recessed LOCOS layer.
Another embodiment relates to a method for manufacturing a semiconductor device including a field effect transistor, the field effect transistor including a gate dielectric layer, a source region and a drain region. A first semi-recessed LOCOS layer is provided between the gate dielectric layer and the drain region, and a second semi-recessed LOCOS layer is provided between the gate dielectric layer and the source region. A first offset impurity layer is provided below the first semi-recessed LOCOS layer, and a second offset impurity layer is provided below the second semi-recessed LOCOS layer. The method includes forming a first recessed section in a region where the first semi-recessed LOCOS layer is to be formed, and forming a second recessed section in a region where the second semi-recessed LOCOS layer is to be formed. The method also includes implanting an impurity in a semiconductor substrate in the first recessed section and in the second recessed section. The method also includes thermally oxidizing the semiconductor substrate to form the first semi-recessed LOCOS layer in the first recessed section and to form the second semi-recessed LOCOS layer in the second recessed section.
Another embodiment relates to a semiconductor device including first and second field effect transistors, each including a gate dielectric layer and source and drain regions. The first and second field effect transistors also each include a first semi-recessed LOCOS layer positioned between the gate dielectric layer and the drain region, and a second semi-recessed LOCOS layer positioned between the gate dielectric layer and the source region. The first and second field effect transistors also each include a first offset impurity layer below the first semi-recessed LOCOS layer, and a second offset impurity layer below the second semi-recessed LOCOS layer. The semiconductor device also includes an element isolation region located between the first and second field effect transistors.


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U.S. application Ser. No. 09/847,071, filed May 1, 2001, having U.S. patent appl. Pub. No. U.S.2002/0003289 A1, and pending claims.

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