Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-08-18
2009-12-15
Ellis, Kevin L (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S731000
Reexamination Certificate
active
07634700
ABSTRACT:
A semiconductor device with test interface, as well as to a method for operating a semiconductor device is disclosed. In one embodiment, in a test operating mode, the semiconductor device is, via a first pin, supplied with a work cycle signal synchronized with a test environment and, via at least one second pin, with test data. In accordance with a first embodiment it is suggested, so as to reduce the number of pins, that the work cycle signal is simultaneously used as test data clock signal.
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Dicke Billig & Czaja, PLLC
Ellis Kevin L
Infineon - Technologies AG
Nguyen Steve
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