Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-12-23
2008-07-15
Chung, Phung M (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S735000, C714S738000
Reexamination Certificate
active
07401276
ABSTRACT:
A semiconductor device includes an output path; an input path; and a test signal generating circuit. The test signal generating circuit generates an input test data signal by changing at least one of an amplitude and a phase of an output test data signal which is generated from a test data in the semiconductor device and transferred on the output path, and supplies the input test data signal onto the input path. The output path and the input path are tested by using the output test data signal and the input test data signal, respectively.
REFERENCES:
patent: 6977538 (2005-12-01), Moll
patent: 7251765 (2007-07-01), Kushiyama et al.
patent: 2002/0174159 (2002-11-01), Laquai
patent: 2002-368827 (2002-12-01), None
Katou Hiromu
Matsumoto Katsuhide
Mitsuishi Masafumi
Sakai Shingo
Souda Masaaki
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