Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2001-06-11
2002-08-06
Graybill, David E. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S786000
Reexamination Certificate
active
06429454
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims benefit of priority under 35 USC 119 based on Japanese Patent Application No. P2000-175484 filed on Jun. 12, 2000, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device with a test circuit and pads that are arranged to easily carry out a test such as a defects analyzing test, and a semiconductor device capable of carrying out a test at intervals of a cycle time set for a semiconductor chip.
2. Description of Related Art
FIG. 1
is a block diagram showing pads arranged on a semiconductor chip in a semiconductor device. The pads and are arranged in a middle part of the chip
102
in order to improve circuit performance. In
FIG. 1
, the pads are input/output (I/O) pads
40
and are connected to probe-card needles or bonding wires
51
, respectively.
To carry out a test such as a defects analyzing test on the semiconductor device, a probe card, for example, is used. The probe card has probe-card needles
51
, which are extended to the pads
40
arranged in the middle part of the chip
102
. As a result, the surface of the chip
102
is covered with the needles
51
, to greatly reduce a space for accepting manual needles for the test, thereby hindering in the test of the defects analyzing.
Since the pads
40
are in the middle part of the chip
102
, the arrangement of
FIG. 1
needs longer bonding wires than a chip that arranges pads along the periphery thereof. The long bonding wires cause signal skew, and narrow gaps among the pads
40
hardly receive the bonding wires.
A circuit board provided with several semiconductor chips frequently employs a boundary scan test circuit for testing wiring shorts or opens. The boundary scan test circuit is configured to test the board at low test frequencies, and therefore, is unable to operate at intervals of a cycle time set for the semiconductor chips installed on the board. Pads formed on these chips are provided with cells such as registers to form a boundary scan chain serving as a test path. To set test data in each pad, the test data must serially be transferred to the pads in synchronization with a test clock signal (TCK), and therefore, setting the test data in all pads needs test clock signal periods whose number is equal to the number of the pads. The test clock signal (TCK) is slower than a clock signal (CK) for semiconductor device operation, and therefore, the boundary scan test circuit is unusable to test logic circuits, etc., that are contained in semiconductor devices on the chip and operate at the clock signal (CK).
SUMMARY OF THE INVENTION
The present invention is to provide a semiconductor device capable of easily accepting manual needles and bonding wires to carry out a test such as a defects analyzing test with the use of, for example, a probe card.
The present invention is further to provide a semiconductor device capable of utilizing a boundary scan test circuit, to test internal circuits such as logic circuits in the semiconductor device according to a clock signal used for device operation.
A semiconductor device according to this invention includes a plurality of input/output pads arranged in a middle part of the semiconductor device, a plurality of registers provided for the input/output pads, respectively, and connected to one another in series to form a serial scan chain, a first pad arranged at the periphery of the semiconductor device and connected to a first one of the registers formed the serial scan chain, the first pad configured to receive externally supplied test data and supply the test data to the registers, a second pad arranged at the periphery of the semiconductor device and connected to a last one of the registers formed the serial scan chain, and a third pad arranged at the periphery of the semiconductor device, the third pad configured to supply an externally supplied first clock signal to the registers.
REFERENCES:
patent: 5386127 (1995-01-01), Furuyama
patent: 5965903 (1999-10-01), Chittipeddi et al.
patent: 6121677 (2000-09-01), Song et al.
patent: 6291835 (2001-09-01), Tsuji et al.
IEEE Standard Test Access Port and Boundary-Scan Architecture, 1149.1, Chapter 1, Feb. 15, 1990.
Hatada Hiroshi
Hirabayashi Osamu
Kameda Yasushi
Otsuka Nobuaki
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