Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-11-29
2008-09-02
Chung, Phung M (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C326S030000
Reexamination Certificate
active
07421631
ABSTRACT:
A semiconductor device includes a signal line, a test load circuit and a termination circuit. The signal line is connected with an input/output node of the semiconductor device. The test load circuit has a test resistor and is provided between the signal line and a first one of power lines to connect the signal line to the first power line through the test resistor in response to a test start signal. The termination circuit has first and second resistors, and is provided between the first power line and a second power line as the other power line to disconnect the signal line from the first and second power lines in response to the test start signal. Also, the test load circuit disconnects the signal line from the first power line in response to a test end signal, and the termination circuit connects the signal line with the first and second power lines through the first and second resistors in response to the test end signal.
REFERENCES:
patent: 6812735 (2004-11-01), Pham
patent: 6961883 (2005-11-01), Tsuji
patent: 7102381 (2006-09-01), Chen et al.
patent: 7193431 (2007-03-01), Miyake et al.
patent: 7197684 (2007-03-01), Fang et al.
patent: 7205788 (2007-04-01), Wang et al.
DDR-2 SDRAM Technology and Design Trends (DesignCon 2003), High Performance System Design Conference, 2003.
Chung Phung M
McGinn IP Law Group PLLC
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