Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-05-19
2003-02-18
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S200000, C438S208000, C438S222000, C438S227000
Reexamination Certificate
active
06521493
ABSTRACT:
BACKGROUND OF THE INVENTION
Trench isolation has been used in the semiconductor industry to reduce circuit topography and better isolate adjacent semiconductor devices. In a typical process of forming shallow trench isolation (STI), a thermally oxidized film is formed on the surface of a shallow trench. The trench is then filled with a dielectric material, for example oxide. A high density plasma process typically deposits the oxide used to fill the trenches and forms isolations. The high density plasma process may create charge trapping along the trench sidewall edge. In addition, it can produce an increase in the hot carrier sensitivity of PMOSFET devices. The enhanced hot carrier sensitivity is due to increased trapping efficiency of electron injection into the STI edge during the hot carrier and can result in the activation of a parasitic edge parasitic PMOSFET device. Thus, there is a need to reduce the STI process induced hot carrier sensitivity in PMOSFETs.
Additionally, a nitride liner is sometimes formed on the thermally oxidized film in the STI. The nitride liner has been shown to be a highly effective oxygen diffusion barrier. Thus, the nitride liner may be formed to prevent oxidation of a silicon sidewall of a collar region of a storage trench. Moreover, the nitride liner prevents dislocations in the active areas of devices.
However, use of the nitride liner can cause some problems. The nitride liner has been shown to be a source of charge trapping, which leads to unacceptable levels of junction leakage in support circuitry. The charge trapping is the result of electron injection into the nitride liner. Charge trapping occurs in the nitride liner mainly due to process induced plasma charging.
The presence of the nitride liner and the resulting increase in electron trapping enhances the hot carrier sensitivity of buried channel PMOSFETs. Many methods of handling charge trapping have been proposed for other types of devices. Most of the methods address the problem by reducing the charge trapped in the nitride liner to improve isolation. For example, U.S. Pat. No. 5,747,866 to Ho et al. describe a structure which limits charge trapping. Ho et al. describe a crystalline RTN nitride liner deposited at greater than 1050° C. to lower the density of trapping centers. However, no satisfactory solutions have been provided for improving hot carrier reliability.
Thus, there is a need for a semiconductor device and manufacturing process that addresses the issue of charge trapping and the degraded hot carrier reliability currently associated with known processes.
SUMMARY OF THE INVENTION
A semiconductor device and method of manufacturing the same are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. After formation of the oxide liner, first regions of the semiconductor substrate are masked, leaving second regions thereof exposed. N-type devices are to be formed in the first regions and p-type devices are to be formed in the second regions. N-type ions may then be implanted into sidewalls of the trenches in the second regions. The mask is stripped and formation of the semiconductor device may be carried out in a conventional manner. The n-type ions are preferably only implanted into sidewalls where PMOSFETs are formed.
REFERENCES:
patent: 4918027 (1990-04-01), Fuse et al.
patent: 5350941 (1994-09-01), Madan
patent: 5795801 (1998-08-01), Lee
patent: 5874346 (1999-02-01), Fulford, Jr. et al.
patent: 5882964 (1999-03-01), Schwalke
patent: 5933722 (1999-08-01), Hong
patent: 5960276 (1999-09-01), Liaw et al.
patent: 5981321 (1999-11-01), Chao
patent: 6051459 (2000-04-01), Gardner et al.
patent: 6143599 (2000-11-01), Kim et al.
patent: 6150204 (2000-11-01), Ahmad et al.
patent: 6214675 (2001-04-01), Cochran et al.
patent: 6228726 (2001-05-01), Liaw
patent: 6245639 (2001-06-01), Tsai et al.
patent: 6297102 (2001-10-01), You et al.
patent: 6306737 (2001-10-01), Mehrad et al.
patent: 6355533 (2002-03-01), Lee
patent: 6380016 (2002-04-01), Kohler
patent: 6410375 (2002-06-01), Lee
patent: 6410378 (2002-06-01), Gonzales
patent: 6413826 (2002-07-01), Kim
patent: 406021398 (1994-01-01), None
patent: 406112419 (1994-04-01), None
patent: 406209080 (1994-07-01), None
patent: 406209081 (1994-07-01), None
Alsmeier Johann
LaRosa Giuseppe
Lukaitis Joseph
Rengarajan Rajesh
C. Li Todd M.
Connolly Bove Lodge & Hutz
Everhart Caridad
Luu Chuong
LandOfFree
Semiconductor device with STI sidewall implant does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device with STI sidewall implant, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device with STI sidewall implant will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3169125