Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-10-27
2001-10-09
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S233000, C438S586000, C438S587000, C438S618000, C257S350000, C257S382000
Reexamination Certificate
active
06300178
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to high integration of a semiconductor device, and more particularly, to a semiconductor device manufactured in a simplified process including a self-aligned contact process and a method of manufacturing the semiconductor device.
Recently, there has been a remarkable progress in integration technology of a semiconductor integrated circuit. The high integration of a semiconductor integrated circuit is generally attained if a micro line, space, and contact pattern are realized by improving a lithographic resolution.
However, alignment technique between layers has been less improved in comparison with resolution technique in lithography. In these circumstances, if alignment allowance is ensured, an entire area size inevitably increases. This is a big problem preventing high integration of the circuit.
In an attempt to overcome the increase in area size, a method has been employed in which a contact is formed in a self-alignment manner to the gate.
For example, manufacturing steps of a semiconductor device conventionally formed by such a method are shown in
FIGS. 1A
to
1
F.
In
FIG. 1A
, a device isolating region
4
is formed in the surface portion of a silicon substrate
2
and a well
2
a
, which has an opposite conductive type to that of the substrate
2
. An n-diffusion layer
6
is formed in the surface portion of the silicon substrate
2
. A p-diffusion layer
8
is formed in a surface portion of the well
2
a
. A gate electrode
12
is formed on the silicon substrate
2
and well
2
a
via a gate oxide film
10
. A reference numeral
14
indicates a cap layer formed of a silicon nitride (SiN) film. Furthermore, a silicon nitride film
16
is formed on the silicon substrate
2
. Note that a gate side wall
18
is formed on both sides of the gate electrode
12
.
As shown in
FIG. 1B
, the silicon nitride film
16
is removed from the surface of the silicon substrate in each of the regions with and without the well
2
a
by RIE (reactive ion etching), and thereafter, impurity ions are implanted into the silicon substrate
2
and the well
2
a
. In this manner, N
+
diffusion layers
20
,
22
and a P
+
diffusion layer
24
serving as a source/drain are formed. Thereafter, an interlayer film
26
is deposited over an entire surface of the silicon substrate
2
.
Subsequently, as shown in
FIG. 1C
, a resist
28
is formed on the interlayer film
26
. However, the resist
28
is not formed on a contact formation region to the source/drain of the substrate
2
. Then, etching is selectively performed to the resultant structure under such a condition that the silicon nitride film
14
is not etched, as shown in
FIG. 1D
, using the resist
28
as a mask. As a result, a contact hole
30
is formed. Accordingly, a contact (to the gate electrode) can be formed even if an alignment allowance is not taken to the gate.
As shown in
FIG. 1E
, a resist
32
is deposited in the contact hole
30
and on the interlayer film
26
excluding the portion in which a contact (to the gate) is to be formed in a later step. Thereafter, a contact hole
34
is formed on the gate using the resist
32
as a mask.
Thereafter, as shown in
FIG. 1F
, metal wiring layers
36
,
38
are formed in each of contact holes
30
,
34
and on the interlayer film
26
.
However, the semiconductor formation method mentioned above requires two contact hole formation steps opposite to each other, that is, the step of forming a contact hole by etching the nitride film formed on the gate (corresponding to
FIG. 1E
) and a step of forming a contact hole without etching the nitride film formed on the gate (corresponding to FIG.
1
D). Since two steps are required for the contact hole formation, the number of processing steps increases.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device and a manufacturing method thereof capable of forming a semiconductor device, which requires a single contact hole formation step, even if a self aligned contact is included in the device.
More specifically, the semiconductor device of the present invention comprises
a gate electrode formed above a semiconductor substrate;
a cap layer having a first contact hole, formed on the gate electrode in a self alignment manner to the gate electrode;
an interlayer film deposited above the semiconductor substrate and the cap layer, and having a second contact hole formed on the first contact hole; and
a wiring layer formed in the first and second contact holes,
wherein the first contact hole and second contact hole are formed by using mutually different masks.
The method of manufacturing a semiconductor device according to the present invention comprises
a first step of processing a laminate structure having a gate insulating film, a gate electrode and a cap layer formed on a substrate, into a gate form in order to form a first conductive-type MIS transistor and a second conductive type MIS transistor;
a second step of etching an entire surface of an insulating film which coats the first conductive type MIS transistor region and a cap layer formed on gate contact portions of the first and second conductive type MIS transistors to substantially expose a substrate surface of the first conductive type MIS transistor and at the same time, to remove a part of the cap layer from the gate contact portions of the first and second conductive type MIS transistors and then, implanting a first conductive type impurity; and
a third step of etching an entire surface of an insulating film which coats the second conductive type MIS transistor region and a cap layer formed on the gate contact portions of the first and second conductive type MIS transistors to substantially expose a substrate surface of the second conductive type MIS transistor and at the same time, to remove remainders of the cap layer on the gate contact portion of the first conductive type MIS transistor and the cap layer on the gate contact portion of the second conductive type MIS transistor, and then, implanting a second conductive type impurity.
Furthermore, the method of manufacturing a semiconductor device according to the present invention comprises
a first step of processing a laminate structure having a gate insulating film, a gate electrode, and a cap layer formed on a substrate into a gate form, in order to form a first conductive type MIS transistor and a second conductive type MIS transistor;
a second step of implanting a first conductive type impurity and a second conductive type impurity into the first conductive type MIS transistor region and the second conductive type MIS transistor region, respectively;
a third step of depositing an insulating layer over an entire surface of the first conductive type MIS transistor region and the second conductive type MIS transistor region;
a fourth step of removing the insulating layer between adjacent gates in a part of an MIS transistor formation region to thereby substantially expose a substrate surface;
a fifth step of selectively forming a plug contact between the adjacent gates;
a sixth step of etching an entire surface of an insulating film which coats the first conductive type MIS transistor region and the cap layer formed on gate contact portions of the first and second conductive type MIS transistors to substantially expose a substrate surface of the first conductive type MIS transistor and at the same time, to remove a part of the cap layer on the gate contact portions of the first and second conductive type MIS transistors, and then, implanting a first conductive type impurity;
a seventh step of etching an entire surface of an insulating film which coats the second conductive type MIS transistor region and the cap layer formed on the gate contact portions of the first and second conductive MIS transistors to substantially expose a substrate surface of the second conductive type MIS transistor and at the same time, to remove remainders of the cap layer on the gate contact portion of the first conductive type MIS tran
Cao Phat X.
Chaudhuri Olik
Kabushiki Kaisha Toshiba
Pillsbury & Winthrop LLP
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