Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-05-01
2001-07-03
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000
Reexamination Certificate
active
06255180
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit manufacturing and, more particularly, to sidewall spacers formed on opposed surfaces of a gate conductor and to a method for forming the sidewall spacers. The spacers can be produced by anisotropically etching a dielectric layer, preferably nitride, using a plasma provided with a carbon-containing species and absent of oxygen, thereby forming, e.g., a nitride sidewall spacer having a relatively thin upper portion and a lower portion that increases in thickness toward the base of the spacer.
2. Description of the Related Art
Fabrication of a multi-level integrated circuit involves numerous processing steps. After impurity regions have been formed within a semiconductor substrate and gate areas defined upon the substrate, interconnect routing is placed across the semiconductor topography and connected to the impurity regions. An interlevel dielectric is formed between the interconnect routing and the substrate to isolate the two levels. Contact areas are placed through the dielectric to electrically link the interconnect routing to select impurity regions extending across the substrate. A second level of interconnect routing may be placed across a second level of interlevel dielectric arranged above the first level of interconnect routing. The first and second levels of interconnect routing may be coupled together by contact structures arranged through the second level of interlevel dielectric. Additional levels of interconnect routing and interlevel dielectric may be formed, if desired.
Sidewall spacers are commonly formed laterally adjacent to the sidewall surfaces of structures arranged upon the semiconductor substrate. For example, during the fabrication of a MOS transistor upon and within the substrate, dielectric sidewall spacers are typically formed upon the opposed sidewall surfaces of a gate conductor spaced above the substrate by a gate dielectric. The presence of the sidewall spacers permit the formation of graded junctions (i.e., active areas) within the substrate on opposite sides of the gate conductor. The graded junctions are formed by first implanting a light concentration of dopant self-aligned to the sidewall surfaces of the gate conductor prior to forming the dielectric sidewall spacers. After the sidewall spacers have been formed, a heavier concentration of dopant self-aligned to the outer lateral surfaces of the spacers may be forwarded into the substrate. The purpose of the first implant is to produce lightly doped drain (“LDD”) sections within the substrate that laterally straddle a channel region underneath the gate conductor. The second implant forms heavily doped source/drain regions within the substrate laterally outside the LDD areas. As a result of the second implant, the source/drain regions are laterally spaced from the channel region by a distance dictated by the thickness of the sidewall spacer and the diffusion length.
Together, the LDD areas and the source/drain regions form graded junctions which increase in dopant concentration in a lateral direction away from the gate conductor. During saturated operation of the ensuing transistor, the LDD areas serve to reduce the so-called maximum electric field, Em, which occurs proximate to the drain. Lowering Em affords protection against detrimental hot carrier effects (“HCE”). HCE is a phenomena by which the kinetic energy of the charge carriers (holes or electrons) is increased as they are accelerated through large potential gradients and subsequently become injected into and trapped within the gate dielectric. As a result of trapped charge accumulating over time in the gate dielectric, an undesirable shift in the threshold voltage, V
T
, of the transistor may occur.
FIG. 1
illustrates the formation of a pair of series-connected MOS transistors
4
and
6
. Series-connected transistors
4
and
6
may be implemented in, e.g., an SRAM memory device. Gate conductors
12
which comprise doped polysilicon are spaced above a semiconductor substrate
10
by a gate dielectric
11
. A dielectric layer
14
composed of, e.g., silicon nitride (“nitride”) may be arranged across each gate conductor
12
Nitride (Si
3
N
4
) sidewall spacers
16
extend laterally from the opposed sidewall surfaces of gate conductors
12
. LDD areas
20
are positioned within substrate
10
directly beneath sidewall spacers
16
. Source/drain regions
18
are arranged within substrate
10
laterally adjacent LDD areas
20
. One of the source/drain regions
18
may be laid out common to both transistor
4
and transistor
6
if, for example, the transistor pairs are coupled in series, or possibly in parallel. The outer surface of each sidewall spacer
16
is substantially perpendicular with the horizontal surface of substrate
10
. Placing LDD areas
20
below, and directly adjacent to, gate conductors
12
can unfortunately lead to short channel effects (“SCE”). The distance between the source-side junction and the drain-side junction is often referred to as the physical channel length. However, during subsequent annealing steps, the dopant species within LDD areas
20
may migrate laterally under gate conductors
12
. As a result of the lateral migration, the actual distance between the source-side and drain-side junctions becomes less than the physical channel length and is often referred to as the effective channel length (“Leff”). Problems associated with SCE, e.g., subthreshold currents, become a factor whenever Leff drops below approximately 1.0 &mgr;m.
The vertical orientation of the outer surfaces of sidewall spacers
16
is a result of the etch technique used to define the spacers. Nitride sidewall spacers
16
are formed by depositing a nitride layer across substrate
10
and gate conductors
12
, allowed by anisotropically etching the nitride layer using a dry, plasma etch technique. The nitride layer may have a thickness of, e.g., 500 Å. A plasma provided with a halocarbon gas, e.g., CF
4
and with O
2
is generated within a reactive-ion etching (“RIE”) reactor during the etch step. It is believed that carbon-containing and oxygen-containing radicals created in the plasma react to form volatile compounds of, e.g., CO. Also, excited F atoms adsorb upon the surface of the nitride layer where they may react with Si
3
N
4
to form volatile compounds, such as SiF
4
. Ions produced in the plasma, being vertically directed, strike the horizontally oriented surfaces of the nitride layer, enhancing the reaction rate at those surfaces and/or the desorption rate of compounds from those surfaces. As such, nitride sidewall spacers
16
which have a lateral thickness similar to that of the originally deposited nitride layer are retained exclusively laterally adjacent to the opposed sidewall surfaces of gate conductors
12
.
FIG. 1
also depicts an interlevel dielectric
22
arranged across transistors
4
and
6
. An ohmic contact
24
has been formed vertically through interlevel dielectric
22
to mutual source/drain region
18
. Contact
24
is interposed between a pair of adjacent spacers
16
, one of which belongs to transistor
4
, and the other of which belongs to transistor
6
. This pair of adjacent spacers
16
have been formed at relatively short distance apart to afford high packing density of transistors
4
and
6
. In fact, the lateral distance between the pair of adjacent spacers
16
of transistors
4
and
6
may be less than the minimum definable feature size of optical lithography. Contact
24
is preferably self-aligned between spacers
20
associated with transistors
4
and
6
. Accordingly, contact
24
is noted herein as a self-aligned contact, and is formed by first lithographically patterning a masking layer (i.e., photoresist) upon regions of interlevel dielectric
22
exclusive of the area to be occupied by contact
24
. The minimum lateral width of the area of interlevel dielectric
22
not covered by the masking layer is thus limited by the constraints of lithography. That exposed area of interleve
Conley & Rose & Tayon P.C.
Cypress Semiconductor Corporation
Daffer Kevin L.
Lindsay Jr. Walter L.
Niebling John F.
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