Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-01-13
2001-02-13
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S781000, C438S782000, C257S758000, C257S760000
Reexamination Certificate
active
06187662
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing of the same. More particularly, the present invention relates to a semiconductor device and a method of manufacturing the same, in which an SOG (spin on glass) film using a low dielectric constant material is formed as a part of an interlayer insulating film.
2. Description of the Related Art
Conventionally, an SOG (spin on glass) insulating film is formed by a spin coating method. The technique using such an SOG film as a part of an interlayer insulating film is frequently used to remove unevenness of the surface of a substrate to be formed due to wiring patterns.
However, in the conventional SOG film using silicate material, there are the following problems. That is, first, {circle around (1)} a crack is easily generated because of large volume shrinkage at the time of a baking process. Second, {circle around (2)} the spin coating method needs to be performed plural times to form a thick SOG film, because the film thickness of the SOG film is at most 200 nm when the spin coating method is performed once. And, third, {circle around (3)} another material having lower dielectric constant is needed to decrease capacitance between wiring patterns, because the dielectric constant of the SOG film is approximately the same as that of a SiO
2
which is formed by a CVD method. For these reasons, a SOG film using HSQ (Hydrogen Silsesquoxane: (HSiO
3/2
)
n
) is proposed to solve the above problems.
FIGS. 1A
to
1
D are cross sectional views of a semiconductor device using an SOG film as a part of an interlayer insulating film in a manufacturing method. This method is proposed in “PLANARIZATION PERFORMANCE OF FLOWABLE OXIDE™ IN THE SUB-0.5 &mgr;m REGIME” (Advanced Metallization and Interconnect Systems for ULSI Applications, 1995, pp. 121-125).
As shown in
FIG. 1A
, a silicon oxide film
502
is formed on a silicon substrate
501
as a lower interlayer insulating film by a plasma CVD method using TEOS (Tetraethoxysilane) as a material source. After metal wiring patterns
503
are formed on the interlayer insulating film
502
, a liner oxide film
504
is formed by a plasma CVD method using TEOS as a material source to cover the metal wiring patterns
503
.
Subsequently, as shown in
FIG. 1B
, HSQ is spin-coated to form an HSG-SOG film
505
. Then, the HSG-SOG film
505
is baked.
Next, as shown in
FIG. 1C
, a silicon oxide film
506
is formed on the HSG-SOG film
505
by a plasma CVD method using TEOS as a material source.
Subsequently, as shown in
FIG. 1D
, the silicon oxide film
506
is flattened by a CMP (chemical mechanical polishing) method to form an upper interlayer insulating film
507
.
It should be noted that similar manufacturing methods are described in Japanese Laid Open Patent Applications (JP-A-Heisei 7-240460 and JP-A-Heisei 8-111458).
However, in the above-mentioned structure of the interlayer insulating films, there is a problem. That is, the dielectric constant of the HSQ film increases because of the escape of moisture from the lower silicon oxide film using the TEOS system material gas at the time of baking of the HSQ film. For a comparison experiment, a comparison sample is formed in which the whole interlayer insulating film is formed of a silicon oxide film by a CVD method using a high density plasma. In both of the conventional sample shown in
FIGS. 1A
to
1
D and the comparison sample, metal wiring patterns are formed to have a space of 0.3 &mgr;m. When the capacitance of the both samples between the metal wiring patterns are measured, the conventional sample has a capacitance between the metal wiring patterns of 110% of that of the capacitance of the comparison sample between the metal wiring patterns. That is, the HSQ film, which should have a low dielectric constant film, has a dielectric constant higher than that of the silicon oxide film. This is because moisture generated from the lower film in case of baking of the HSQ film invades the HSQ film, so that Si—H couplings decrease and Si—OH couplings increase. The dielectric constant of the HSQ film increases as the Si—H couplings decrease and the Si—OH couplings increase. It is known that the dielectric constant of the HSQ film becomes high when the HSQ film is baked in an atmosphere containing oxygen. Therefore, it could be considered that the same phenomenon occurs.
When the HSQ film is covered by an upper insulating film, the HSQ film is not influenced so much by the upper insulating film, compared with the lower insulating film. However, in a portion of the HSQ film contacting the upper insulating film, the Si—OH couplings increase and the Si—H couplings decrease.
SUMMARY OF THE INVENTION
The present invention is accomplished to solve the above mentioned problems. Therefore, an object of the present invention is to provide a semiconductor device in which it can be prevented that Si—H couplings in a low dielectric constant film such as a HSQ film decrease due to moisture supplied from another insulating film contacting the low dielectric constant film in a baking process.
Another object of the present invention is to provide a semiconductor device in which the increase of a dielectric constant of a low dielectric constant film such as a HSQ film can be prevented.
Still another object of the present invention is to provide a method of manufacturing the above semiconductor devices.
In order to achieve an aspect of the present invention, a semiconductor device includes a first insulating film formed on a semiconductor substrate. Wiring patterns are partially formed on the first interlayer insulating film. A second insulating film is formed to cover the first insulating film and the wiring patterns. A third insulating film is formed on the second insulating film. In this case, at least an upper surface portion of the first insulating film has a moisture containing percentage lower than that of the second insulating film.
The semiconductor device may further include a liner insulating film formed to cover the first insulating film and the wiring patterns. In this case, the second insulating film is formed on the liner insulating film.
The second insulating film has a relative dielectric constant smaller than 3.5, and the second insulating film includes Si—H couplings.
The upper surface portion of the first insulating film has a moisture containing percentage lower than 0.02 wt %. In this case, the second insulating film is formed of one of a silicon oxide film containing a PSG film and a BPSG film, a silicon oxide nitride (SiON) film, a silicon nitride film, and a fluorine containing silicon oxide film.
Also, it is desirable that at least a lower surface portion of the third insulating film has a moisture containing percentage lower than 0.02 wt %. The third insulating film is formed of one of a silicon oxide film containing a PSG film and a BPSG film, a silicon oxide nitride (SiON) film, a silicon nitride film, and a fluorine containing silicon oxide film.
In order to achieve another aspect of the present invention, a method of manufacturing a semiconductor device, includes the steps of:
forming a first insulating film on a semiconductor substrate such that at least an upper surface portion of the first insulating film has a first moisture containing percentage;
forming wiring patterns on the first insulating film;
forming a second insulating film to cover the first insulating film and the wiring patterns, the second insulating film having a second moisture containing percentage lower than the first moisture containing percentage; and
forming a third insulating film formed on the second insulating film.
In this case, the second insulating film is formed by a spin-coating method using HSQ (hydrogen silisesquoxane: (HSiO
3/2
)
n
) or polysilazane. In order to form the second insulating film, a first heat treatment is performed to the second insulating film formed by the spin-coating method at a predetermined temperature for a predetermined time. Thus, the second mo
Oda Noriaki
Usami Tatsuya
Hayes, Soloway, Hennessey Grossman & Hage, P.C.
NEC Corporation
Smith Matthew
Yevsikov Victor
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