Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-06-16
2002-10-29
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S900000, C257S310000, C257S774000
Reexamination Certificate
active
06472700
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and methods of manufacturing thereof. More particularly, the present invention relates to a semiconductor device with an isolation insulator capable of being miniaturized and highly integrated without deterioration in the electric characteristics, and a method of manufacturing thereof.
2. Description of the Background Art
Semiconductor devices represented such as by DRAMs (Dynamic Random Access Memories) are conventionally known.
FIG. 31
is a schematic cross sectional view showing a conventional semiconductor device.
Referring to
FIG. 31
, the semiconductor device includes a field effect transistor formed at a main surface of a semiconductor substrate
101
. At the main surface of semiconductor substrate
101
, an LOCOS (Local Oxidation of Silicon) isolation oxide film
129
is formed to isolate conductive regions. The source/drain regions
103
a
,
103
b
of the field effect transistors are formed in the conductive regions. In channel regions adjacent to source/drain regions
103
a
,
103
b
, gate insulation films
104
a
,
104
b
are formed on the main surface of semiconductor substrate
101
. Gate electrodes
105
a
to
105
c
are formed on gate insulation films
104
a
,
104
b
and isolation oxide film
129
. Gate electrode side walls
107
a
to
107
d
are formed on the side surfaces of gate electrodes
105
a
to
105
c
. An interlayer insulation film
109
is formed on gate electrodes
105
a
to
105
c
and gate electrode sidewalls
107
a
to
107
d
. In a region on source/drain regions
103
a
,
103
b
, contact holes
110
a
,
110
b
are formed in interlayer insulation film
109
. In contact holes
110
a
,
110
b
and on interlayer insulation film
109
, interconnections
111
a
,
111
b
are formed to electrically connect to source/drain regions
103
a
,
103
b
. A second interlayer insulation film
112
is formed on interlayer insulation film
109
and interconnections
111
a
,
111
b.
In recent years, miniaturization and integration of semiconductor devices have increasingly been demanded. Recently, the gate length of a field effect transistor in the semiconductor device as shown in
FIG. 31
has been required to be as small as about 0.18 &mgr;m. The inventors found out that problems as described below occur as semiconductors continue to be highly integrated and miniaturized. Referring to
FIG. 32
, the problems will be described in detail below.
FIG. 32
is a schematic cross sectional view for describing a method of manufacturing the semiconductor device shown in FIG.
31
. As shown in
FIG. 32
, isolation oxide film
129
and source/drain regions
103
a
,
103
b
are formed at the main surface of semiconductor device
101
by a method similar to conventional methods of manufacturing a semiconductor device. Similarly, gate insulation films
104
a
,
104
b
, gate electrodes
105
a
to
105
c
, gate electrode sidewalls
107
a
to
107
d
and first interlayer insulation film
109
are formed on the main surface of semiconductor substrate
101
. Then, a resist pattern
123
is formed on interlayer insulation film
109
. By removing interlayer insulation film
109
through etching using resist pattern
123
as a mask, contact holes
110
a
,
110
b
are formed.
When the gate length of the field effect transistor is as fine as 0.18 &mgr;m, the positioning accuracy of contact holes
110
a
,
110
b
are required to be higher than ever. However, the positions of contact holes
10
a
,
110
b
may be shifted from their prescribed positions such as by mask alignment errors in forming resist pattern
123
and the like. As shown in
FIG. 32
, ends
134
a
,
134
b
of isolation oxide film
129
may be removed during etching for forming contact holes
110
a
,
110
b.
After the step shown in
FIG. 32
, resist pattern
123
is removed. Then, interconnections
111
a
,
111
b
(see
FIG. 33
) formed of doped polysilicon, for example, are formed in contact holes
110
a
,
110
b
and on first interlayer insulation film
109
. By forming second interlayer insulation film
112
(see
FIG. 33
) on interconnections
111
a
,
111
b
and first interlayer insulation film
109
, the semiconductor device as shown in
FIG. 33
can be obtained. Here,
FIG. 33
is a schematic cross sectional view showing the semiconductor device manufactured by the manufacturing method shown in FIG.
32
.
Referring to
FIG. 33
, the ends of isolation oxide film
129
are partially removed during etching for forming contact holes
110
a
,
110
b
, and the width W of isolation oxide film
129
is made smaller than a designed value. Here, a parasitic transistor is formed of which gate electrode is gate electrode
105
c
, which gate insulation film is isolation oxide film
129
, and which source/drain regions are source/drain regions
103
a
,
103
b
. The width of isolation oxide film
129
corresponds to the gate length of the parasitic transistor. Since the gate length is made smaller than a desired value, the threshold voltage of the parasitic transistor becomes lower than a designed value. Accordingly, a junction leakage current in this semiconductor device becomes undesirably larger than a designed value. A large junction leakage current causes a malfunction of a semiconductor device circuit as an example, a cause of deteriorating the electric characteristics of a semiconductor device. These problems have become serious as semiconductor devices continue to be miniaturized and integrated.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a semiconductor device capable of suppressing increase in the junction leakage current and preventing deterioration in the electric characteristics even when the device is miniaturized.
Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of suppressing increase in the junction leakage current and preventing deterioration in the electric characteristics even when the device is miniaturized.
A semiconductor device according to a first aspect of the present invention includes a semiconductor substrate, an isolation insulator, a gate electrode, a coating film, an interlayer insulation film, and a sidewall coating film. The semiconductor substrate has a main surface. The isolation insulator is formed at the main surface of the semiconductor substrate and isolates a conductive region. The gate electrode is formed in the conductive region. The coating film is formed on the isolation insulator, has a sidewall, and has a film thickness of at most that of the gate electrode. The interlayer insulation film is formed on the coating film. The sidewall coating film is formed on the sidewall of the coating film and includes a material having an etching rate different from that of the interlayer insulation film.
Accordingly, even when a contact hole is to be formed in a region adjacent to the sidewall coating film by removing part of the interlayer insulation film, the sidewall coating film serves as a protection film for preventing damage to the isolation insulator by etching. Thus, even if the position of a mask for etching is varied in the step of forming the contact hole, damage to the isolation insulator by etching can be prevented. As a result, removal of part of the isolation insulator by etching can be prevented, which can prevent reduction in the width of the isolation insulator. Thus, increase in the junction leakage current in the semiconductor device, which is due to reduction in the width of the isolation insulator, can be prevented. Therefore, deterioration in the electric characteristics of a semiconductor device, which is due to increase in the junction leakage current, can be prevented.
If the sidewall of the contact hole has its bottom partially including the sidewall coating film, the bottom area of the contact hole can be changed by changing the film thickness of the sidewall coating film. The film thickness of the sidewall coating film can be changed by changing the height of the coati
Fujisawa Masahiko
Teramoto Akinobu
Wakao Kazutoshi
Mitsubishi Denki & Kabushiki Kaisha
Williams Alexander O.
LandOfFree
Semiconductor device with isolation insulator, interlayer... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device with isolation insulator, interlayer..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device with isolation insulator, interlayer... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2988707