Semiconductor device with improved overlay margin and method...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S216000, C257S297000, C257S328000, C257SE21655, C257SE21657

Reexamination Certificate

active

07414279

ABSTRACT:
Semiconductor devices with an improved overlay margin and methods of manufacturing the same are provided. In one aspect, a method includes forming a buried bit line in a substrate; forming an isolation layer in the substrate to define an active region, the isolation layer being parallel to the bit line without overlapping the bit line; and forming a gate line including a gate pattern and a conductive line by forming the gate pattern in the active region and forming a conductive line that extends at a right angle to the bit line across the active region and is electrically connected to the gate pattern disposed thereunder. The gate pattern and the conductive line can be integrally formed.

REFERENCES:
patent: 5828094 (1998-10-01), Lee
patent: 6541828 (2003-04-01), Chang
patent: 6555866 (2003-04-01), Kuo
patent: 6593613 (2003-07-01), Alsmeier et al.
patent: 6674120 (2004-01-01), Fujiwara
patent: 010056239 (2001-07-01), None

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