Semiconductor device with flexible redundancy system

Static information storage and retrieval – Read/write circuit – Bad bit

Reexamination Certificate

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C365S189070

Reexamination Certificate

active

06865124

ABSTRACT:
A memory cell array includes spare elements for saving a defective cell. Fuse sets each contain a defective address and mapping information indicative of the relationship between the fuse sets and the spare elements. When the defective address matches an input address, each fuse set outputs a signal for activating a corresponding spare element. The number of the fuse sets within a chip is smaller than the number of the spare elements.

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