Finfet gate formation using reverse trim of dummy gate

Details Finfet gate formation using reverse trim of dummy gate Finfet gate formation using reverse trim of dummy gate

2005-03-08

2005-03-08

Chen, Jack (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S283000, C438S589000

Reexamination Certificate

active

06864164

ABSTRACT:
A method of forming a gate electrode for a fin field effect transistor (FinFET) includes forming a fin on a substrate and forming an oxide layer over the fin. The method further includes forming a carbon layer over the oxide layer and forming a trench in the oxide layer and the carbon layer, where the trench crosses over the fin. The method also includes filling the trench with a material to form the gate electrode.

REFERENCES:
patent: 5801397 (1998-09-01), Cunningham
patent: 5960270 (1999-09-01), Misra et al.
patent: 6265256 (2001-07-01), An et al.
patent: 6303447 (2001-10-01), Chhagan et al.
patent: 6342410 (2002-01-01), Yu
patent: 6396108 (2002-05-01), Krivokapic et al.
patent: 6406951 (2002-06-01), Yu
patent: 6413802 (2002-07-01), Hu et al.
patent: 6458662 (2002-10-01), Yu
patent: 6475890 (2002-11-01), Yu
patent: 6515320 (2003-02-01), Azuma et al.
patent: 6525403 (2003-02-01), Inaba et al.
patent: 6551885 (2003-04-01), Yu
patent: 6551886 (2003-04-01), Yu
patent: 6562665 (2003-05-01), Yu
patent: 6583469 (2003-06-01), Fried et al.
patent: 6645797 (2003-11-01), Buynoski et al.
patent: 20020153587 (2002-10-01), Adkisson et al.
patent: 20030111686 (2003-06-01), Nowak
patent: 20030113970 (2003-06-01), Fried et al.
patent: 20030141525 (2003-07-01), Nowak
patent: 20030151077 (2003-08-01), Mathew et al.
patent: WO 03015182 (2003-02-01), None
Digh Hisamoto et al., “FinFET—A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
Yang-Kyu Choi et al., “Sub-20nm CMOS FinFET Technologies,” 2001 IEEE, IEDM, pp. 421-424.
Xuejue Huang et al., “Sub-50 nm P-Channel FinFET,” IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001, pp. 880-886.
Xuejue Huang et al., “Sub 50-nm FinFET: PMOS,” 1999 IEEE, IEDM, pp. 67-70.
Yang-Kyu Choi et al., “Nanoscale CMOS Spacer FinFET for the Terabit Era,” IEEE Electron Device Letters, vol. 23, No. 1, Jan. 2002, pp. 25-27.
Co-pending U.S. Appl. No. 10/310,777 entitled “Damascene Gate Process with Sacrificial Oxide in Semiconductor Devices,” filed Dec. 6, 2002, 19 page specification, 10 sheets of drawings.
Copy of co-pending Appl. No. 10/459,589; entitled “FinFET Gate Formation Using Reverse Trim and Oxide Polish”; filed on Jun. 12, 2003; 45 pages.
Copy of co-pending Appl. No. 10/645,577; entitled Sacrificial Oxide Protection During Dummy Gate Removal in Damascene Gate Process in Semiconductor Devices; filed on Aug. 22, 2003; 28 pages.
Copy of co-pending Appl. No. 10/720,166, entitled “Damascene Gate Process with Sacrificial Oxide in Semiconductor Devices” and Preliminary Amendment filed in 10/720,166 on Nov. 25, 2003; 41 pages.
Copy of U.S. Appl. No. 10/754,559; filed Jan. 12, 2004; entitled: “Damascene Tri-Gate Finfet”; 28 pages.
Stephen H. Tang et al., “Comparison of Short-Channel Effect and Offstate Leakage in Symmetric vs. Asymmetric Double Gate MOSFETs”, IEEE International SOI Conference, Oct. 2000, pp. 120-121.

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