Semiconductor device with field shield electrode

Details Semiconductor device with field shield electrode Semiconductor device with field shield electrode

1997-12-15

2001-02-20

Abraham, Fetsum (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S288000, C257S324000, C257S325000, C257S296000, C257S350000, C257S351000, C257S368000, C257S392000, C257S393000

Reexamination Certificate

active

06191450

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method therefor, and more particularly to a semiconductor device with field-shield isolation structure and a manufacturing method therefor.
2. Description of the Background Art
FIG. 82
is a sectional perspective view of a semiconductor device M
90
with field-shield isolation structure in the background art of the present invention. This is an SOI (Semiconductor-On-Isolation) type semiconductor device using an SOI substrate which has a film-like semiconductor layer, i.e., an SOI layer on an insulating substrate as a semiconductor substrate in which a transistor element is provided.
In the semiconductor device M
90
, as shown in
FIG. 82
, a silicon semiconductor layer is formed as an SOI layer
3
on an insulating substrate constituted of a supporting substrate
1
and a buried oxide film
2
. The SOI layer
3
includes a region where each of many NMOS transistors is formed (referred to as “NMOS region” hereinafter) and a region where each of many PMOS transistors is formed (“PMOS region” hereinafter). Plate-like field-shield (gate) electrodes
5
(“FS electrode” hereinafter) are each formed in a boundary between these element regions to electrically isolating these element regions from each other.
The FS electrodes
5
are disposed in parallel at a predetermined interval to define an active region in each element region. Each FS electrode
5
is covered with a field-shield insulating layer
4
(“FS insulating layer” hereinafter) and a gate electrode
6
is disposed on the active region, extending onto the two parallel FS insulating layers
4
. A gate oxide film
10
is formed between the gate electrode
6
and the active region. The FS insulating layer
4
is made of an oxide, providing electrical isolation between the FS electrode
5
and the gate electrode
6
.
A drain electrode and a source electrode (both not shown), i.e., main electrodes are connected to a source/drain layer (now shown) in the SOI layer
3
through a contact hole
7
provided in a not-shown insulating layer, and a gate interconnection (not shown) is connected to the gate electrode
6
through a contact hole
8
.
The contact hole
9
connected to the body contact electrode (not shown) penetrates the FS electrode
5
to be connected to the SOI layer
3
in
FIG. 82
, but the contact hole
9
may be provided externally of the FS electrode
5
.
In the semiconductor device M
90
, the FS electrode
5
is reversely biased to cut off an isolation region in the SOI layer
3
, and as a result, an electrical isolation between the element regions is established. For isolation between the element regions, besides this structure, a LOCOS structure which provides an isolation by selectively oxidizing the SOI layer
3
or a mesa isolation structure which separates the element regions by selectively etching the SOI layer
3
.
Formation of the LOCOS structure or the mesa isolation structure, however, needs a local oxidation or a local etching of the SOI layer
3
, causing local concentration of stress in the SOI layer
3
. As a result, there arises a problem in terms of reliability of device, such as generation of leak current. In contrast, formation of the field-shield isolation structure needs no local oxidation or local etching. This avoids stress concentration, suppressing leak current, to ensure relatively high reliability.
The following prior-art documents have been found by searching. Outlines thereof will be presented below. In Japanese Patent Application Laid Open Gazette 8-162523, a cap insulating film made of a silicon nitride film is provided on a shield gate electrode and instead of a side wall insulating film, a side surface of the shield gate electrode is thermally oxidized.
In Japanese Patent Application Laid Open Gazette 7-201967, a side surface of a polycrystalline silicon film is thermally oxidized to reduce the width of a field-shield electrode made of a polycrystalline silicon film.
In Japanese Patent Application Laid Open Gazette 8-31928, a shield gate oxide film, a silicon nitride film and a polycrystalline silicon film are sequentially formed.
In Japanese Patent Application Laid Open Gazette 6-302779, a shield plate electrode is formed on an ONO film.
Japanese Patent Application Laid Open Gazettes 7-283300 and 9-27600, an upper surface and a side surface of a shield electrode is covered with a nitride film.
In the background-art field-shield isolation structure, various problems are left unsolved in terms of reliability due to its structure and its manufacturing method.
Showing steps for manufacturing the field-shield isolation structure in the background art with reference to
FIGS. 83
to
101
, these problems will be discussed below.
First, as shown in
FIG. 83
, an oxide film OF
1
, a polysilicon layer PS
1
doped with an impurity (e.g., phosphorus) and an oxide film OF
2
are sequentially formed on a surface of the SOI layer
3
in the SOI substrate. The SOI layer
3
has a thickness of about 1000 Å, the oxide film OF
1
has a thickness of about 200 Å, the polysilicon layer PSI has a thickness of about 500 Å and the oxide film OF
2
has a thickness of about 1000 Å.
Next, in the step of
FIG. 84
, a patterned resist mask R
1
is formed on the oxide film OF
2
.
In the step of
FIG. 85
, with the resist mask R
1
used as a mask, the oxide film OF
2
and the polysilicon layer PS
1
are selectively removed by anisotropic etching (dry etching), to form an FS upper oxide film
41
(the first oxide film) and an FS electrode
5
.
Subsequently, in the step of
FIG. 86
, an oxide film OF
3
is formed so as to cover the oxide film OF
1
, the FS upper oxide film
41
and the FS electrode
5
. The oxide film OF
3
has a thickness of 1500 to 2000 Å.
In the step of
FIG. 87
, the oxide film OF
3
is removed by anisotropic etching (dry etching), to form a side wall oxide film
42
(the second oxide film) on side surfaces of the FS upper oxide film
41
and the FS electrode
5
.
After that, in the step of
FIG. 88
, the oxide film OF
1
is removed. The oxide film OF
1
serves as a protective film for protecting the source/drain region from exposure to the plasma of the dry etching, and is removed by wet etching. Through this step, the oxide film OF
1
remains only below the FS electrode
5
and the side wall oxide film
42
, becoming an FS gate oxide film
43
. The FS upper oxide film
41
, the side wall oxide film
42
and the FS gate oxide film
43
constitute the FS insulating layer
4
. Together with the oxide film OF
1
, the FS upper oxide film
41
and the side wall oxide film
42
are etched at the same time, to become thinner. As the FS upper oxide film
41
becomes thinner, the parasitic capacitance between the FS electrode
5
and the gate electrode
6
increases, to cause degradation of operating speed of the device and increase likelihood of short circuits between these electrodes.
In the step of
FIG. 89
, an oxide film OF
4
which is to become the gate oxide film
10
on the surface of the SOI layer
3
by thermal oxidation. In forming the oxide film OF
4
, the oxygen used as an oxidant goes through the FS upper oxide film
41
, the side wall oxide film
42
and the FS gate oxide film
43
to oxidize the FS electrode
5
. The FS electrode
5
is a doped polysilicon layer which is easily oxidize and becomes thinner in substantial thickness by oxidation.
As the FS electrode
5
becomes thinner, its electrical resistance increases and there is a possibility of not achieving the desired performance during device operation with insufficient effect of field-shield isolation.
Further, the oxygen reaching the bottom of the FS electrode
5
oxidizes an edge portion of the FS electrode
5
, and as it also oxidizes the SOI layer
3
beneath the side wall oxide film
42
, an edge portion of the FS gate oxide film
43
becomes thicker and the edge portion of the FS electrode
5
is warped up. That's because an edge portion is more oxidized and a

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