Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-02-26
2004-11-16
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S286000, C438S588000, C438S981000
Reexamination Certificate
active
06818514
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device, more particularly a device having dual gate oxides and/or a guard ring separating two active regions.
With the advances in semiconductor technology, a semiconductor device is provided increasingly with multiple functions. Such a multi-functional device is provided with different circuitries that may operate in different voltage regimes within the same chip.
In addition, as the technology advances and the devices are scaled down, the operational voltage decreases as well, particularly for high density devices. However, these high density devices, operating a low voltage, generally need to interface with other devices that may use higher Vcc. Accordingly, the high density devices are provided with an I/O circuitry to interface with the external devices having higher Vcc. For example, a high density device is provided with first circuitry configured to operate at a high voltage, e.g., about 5 volts, and second circuitry configured to operate at a low voltage, e.g., about 3.3 volts.
For optimal operation, the devices having two different voltage regimes are provided generally with dual gate oxides: a thick gate oxide configured for the high voltage and a thin gate oxide configured for the low voltage. Therefore, employing these type of combined VLSI circuits requires a technique for fabricating gate oxide layers having a significant thickness difference for diverse uses within the same silicon substrate.
BRIEF SUMMARY OF THE INVENTION
In one embodiment, a method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. A nitride layer overlying the first and second active regions is formed. An oxide layer overlying the nitride layer is formed. A first portion of the oxide layer overlying the first active region is removed to expose a first portion of the nitride layer leaving a second portion of the nitride layer that is overlying the second active region intact. Thereafter, a first gate oxide having a first thickness is formed on the first active region, the first gate oxide having a first edge facing the first isolation structure and a second edge facing the second isolation structure. The first edge is separated from the first isolation structure by a first distance. The second edge is separated from the second isolation structure by a second distance. Thereafter, a second gate oxide having a second thickness is formed on the second active region, the second thickness being different than the first thickness.
Another embodiment is directed to a method for making a semiconductor device having a first active region and a second active region. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. The method includes providing first, second, and third isolation structures defining the first and second active regions on a substrate; providing a separation structure between the second and third isolation structures, the second and third isolation structures and the separation structure being provided between the first and second active regions; forming a nitride layer overlying the first and second active regions of the substrate; forming an oxide layer overlying the nitride layer; removing a first portion of the oxide layer overlying the first active region to expose a first portion of the nitride layer; removing the exposed first portion of the nitride layer while leaving a second portion of the nitride layer that is overlying the second active region intact; thereafter, forming a first gate oxide having a first thickness on the first active region and being configured to handle the first voltage; and thereafter, forming a second gate oxide having a second thickness on the second active region and being configured to handle the second voltage, the second thickness being different than the first thickness.
In yet another embodiment, a method for making a semiconductor device having a first active region and a second active region is disclosed, the first active region using a first operational voltage and the second active region using a second operational voltage that is different from the first voltage. The method includes providing first, second, and third shallow trench isolation (“STI”) structures defining the first and second active regions on a silicon substrate; providing a guard ring between the second and third STI structures, the guard ring enclosing the first active region; forming a nitride layer overlying the first and second active regions; forming an oxide layer overlying the nitride layer; removing a first portion of the oxide layer overlying the first active region to expose a first portion of the nitride layer; removing the exposed first portion of the nitride layer using a wet etch method while leaving a second portion of the nitride layer overlying the second active region intact; thereafter, forming a first gate oxide having a first thickness on the first active region, the first gate oxide having a first edge facing the first isolation structure and a second edge facing the second isolation structure, the first edge being separated from the first isolation structure by a first distance and the second edge being separated from the second isolation structure by a second distance; and thereafter, forming a second gate oxide having a second thickness on the second active region, the second thickness being different than the first thickness.
REFERENCES:
patent: 6091109 (2000-07-01), Hasegawa
patent: 6165918 (2000-12-01), Jia et al.
patent: 6228721 (2001-05-01), Yu
patent: 6271092 (2001-08-01), Lee
patent: 6420222 (2002-07-01), Watanabe
patent: 6686246 (2004-02-01), Gonzalez
Chien Choong Shiau
Inoue Naoto
Kim Inki
Kim Sang Yeon
Lam Zadig
Picardat Kevin M.
SilTerra Malaysia Sdn. Bhd.
Townsend and Townsend / and Crew LLP
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