Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2011-07-05
2011-07-05
Maldonado, Julio J (Department: 2823)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S624000, C438S638000, C257SE21026, C257SE21038, C257SE21259, C257SE21492, C349S085000
Reexamination Certificate
active
07972964
ABSTRACT:
A plurality of gate lines are formed on a substrate. After depositing a gate insulating layer, a semiconductor layer and a doped amorphous silicon layer are sequentially formed thereon. A lower insulating layer made of silicon nitride and an upper insulating layer made of a photosensitive organic material are deposited thereon after forming data lines and drain electrodes. The upper insulating layer is patterned to form an unevenness pattern on its surface and contact holes on the drain electrodes. The lower insulating layer is patterned together with the gate insulating layer using a photoresist pattern having apertures located in the contact holes to form other contact holes respectively exposing the drain electrodes, portions of the gate lines, and portions of the data lines. After forming transparent electrodes and contact assistants respectively connected to the drain electrodes and the gate and the data lines through the contact holes, reflecting electrodes having apertures are formed on the transparent electrodes.
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F. Chau & Associates LLC
Maldonado Julio J
Samsung Electronics Co,. Ltd.
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