Semiconductor device with common pin for address and data

Details Semiconductor device with common pin for address and data Semiconductor device with common pin for address and data

1999-04-02

2001-08-07

Nguyen, Hiep T. (Department: 2185)

Static information storage and retrieval

Read/write circuit

Plural use of terminal

C365S189020, C365S189050, C365S191000, C365S194000, C365S230020, C711S211000, C711S154000

Reexamination Certificate

active

06272053

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device; and, more particular, to DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory) having a common pin for address and data signals.
DESCRIPTION OF THE PRIOR ART
Generally, one of the remarkable features is for the SRAM device to be used as a memory device in the mobile telecommunications. The main issue associated with the SRAM device is put on the reduction of power and its package size. Since the mobile telecommunications have used a battery as a power supply, it is very important to implement the low power consumption in the used telecommunication equipment. Furthermore, with the miniaturization of the portable telephones, it is required to reduce the size of memory package as well as other elements.
Recently, the many efforts have been made for reducing the operation voltage in the SRAM device and also new packaging technology, such a CSP (Chip Scale Package), has been developed for decreasing the size of the package.
FIG. 1
is a block diagram illustrating package balls in the conventional 1M, 2M and 4M SRAM devices. As shown in
FIG. 1
, a SRAM package of the conventional CSP has 48(6×8) balls corresponding to the input/output pins and the distance between the balls is approximately 0.75 &mgr;m. However, with the increase of integration in the SRAM device, the conventional CSP may increase the size of the package because of a number of balls. That is, since it is inevitable that the chip in the conventional CSP should be enlarged more than the ball grid area, it is very difficult to minimize the chip size of devices with low cost in the production of the memory device.
Although the decrease of distance between the balls may solve such an integration problem, it is very difficult to reduce the distance between the balls because other problems can occur in the package. Particularly, the width between metal wires is limited to a predetermined distance in the PCB (Printed Circuit Board) of the portable telephones. In the case of a chip having 48 balls, the distance between the balls is limited to more than 0.75 &mgr;m for connecting all the balls to metal wires. Furthermore, the 48-ball CSP should be used only in 4M SRAMs or less because of the small number of ball. Accordingly, when 8M SRAM devices prevail in various applications in the future, a new standard for the CSP must be established.
FIG. 2
a
is a block diagram illustrating data input/output pad and address pad in the conventional SRAM and
FIG. 2
b
is a timing chart illustrating a read cycle and a write cycle in
FIG. 2
a
. Referring to
FIGS. 2
a
and
2
b
, at a write operation in the conventional SRAM, data from a data input/output pad (I/O pad) are inputted into selected memory cells via an input buffer
20
, which is controlled by a write enable signal /WE. At a read operation for reading out stored data in the memory cells, the output data are outputted to the data input/output pad through an output buffer
22
, which is controlled by the write enable signal /WE and a read enable signal /OE. In similar, addresses from an address input pad are inputted into a decoder via an input buffer
24
. In
FIG. 2
b
, /CS denotes a chip enable signal. The signal transmission between an external circuit and an internal memory is carried out through the buffers in response to various control signals. Typically, the buffer exists on each of the signal paths.
Referring now to
FIG. 2
c
showing the input and output buffers in
FIG. 2
a
, the output buffer
20
includes a control part receiving the write and output control signals /WE and /OE and a CMOS inverter, and also the input buffers
22
and
24
include pull-up device and pull-down devices which perform a logic OR operation. The input buffer
22
connected to the I/O pad is controlled by the write enable signal /WE.
However, since this conventional memory device, such an SRAM, must have a separate pad for each of data and address signals, the number of pin may increase with the reduction of its integration. Furthermore, this increase in the number of pin simultaneously appears in other memory devices, such as SRAM, DRAM and ROM.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a semiconductor memory device capable of decreasing the size of its package with the reduced number of pin.
In accordance with an aspect of the present invention, there is provided a signal processing device receiving signals from an external circuit and outputting processed signals to the external circuit, the signal processing device comprising: at least one common signal input means for receiving more than two kinds of signals; a plurality of signals paths connected to the common signal input means; and a control means for controlling the signals paths in response to a plurality of control signals from the external circuit.
In accordance with another aspect of the present invention, there is provided a semiconductor memory device comprising: at least one common signal input terminal for receiving data signals and address signals; a first input terminal for receiving a read enable signal; a second input terminal for receiving a write enable signal; a third input terminal for receiving a first control signal to control a signal transferring path according to kinds of signals on the common signal input terminal, wherein the signals on the common signal input terminal are the data signals or the address signals; a data input means coupled to the common signal input terminal for inputting the data signals to memory cells in response to the write enable signal and the first control signal; and an address input means coupled to the common signal input terminal for inputting the address signals to a decoding means in response to the write enable signal and the first control signal.
In accordance with still another aspect of the present invention, there is provided a semiconductor memory circuit comprising: at least one common signal input terminal for receiving data signals and address signals, wherein the common signal input terminal is coupled to a plurality signal paths; and a signal path selecting means for selecting one of the plurality signal paths in response to a write enable signal, a read enable and a control signal from a memory controller. The signal path selecting means comprises a plurality of buffers on the signal paths and the signal path selecting mean selects one of the buffers in response to a write enable signal, a read enable and a control signal from a memory controller. Also, the buffer further comprises a plurality of latch circuits and wherein the latched signals are selected by a chip enable signal, the write enable signal and the control signal from a memory controller.


REFERENCES:
patent: 5249160 (1993-09-01), Wu et al.
patent: 5640361 (1997-06-01), Hessel
patent: 5793990 (1998-08-01), Jirgal et al.
patent: 5845108 (1998-12-01), Yoo et al.
patent: 6044412 (2000-03-01), Evoy
patent: 07-21768 (1995-01-01), None

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