Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
1996-06-26
2001-03-20
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
C257S668000, C257S786000, C257S207000
Reexamination Certificate
active
06204567
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a display driver integrated circuit or IC (such as an LCD driver), a multi-bit driver IC (such as a printer driver IC), a multiple input/output IC (such as a sensor interface IC), a gate array, and the like. More particularly, the present invention relates to a semiconductor device in which circuit cells of the same circuit configuration and input or output electrodes are arrayed in pairs. Also, the invention relates to a data input/output device using such a semiconductor device.
BACKGROUND OF THE INVENTION
The prior art common driver semiconductor integrated circuit for a liquid crystal display (LCD) is shown in FIG.
9
and comprises an N-bit shift register circuit portion
3
consisting of N stages, an N-bit latch circuit portion
5
, an N-bit level shift circuit portion
6
, and an N-bit driver circuit portion
7
. A data signal input electrode
1
and a clock electrode
2
are connected with the shift register circuit portion
3
. Data signals or display data signals D
IN
are applied to the shift register circuit portion
3
via the input electrode
1
. Clock pulses CP are applied to the shift register circuit portion
3
via the clock electrode
2
. The data signals D
IN
provided to the shift register circuit portion
3
via the input electrode
1
are transmitted from the first stage
3
1
to the final stage
3
N
serially every N clock pulses in synchronism with the clock pulses CP. The output Q
N
appearing at the final stage
3
N
is supplied as output data signal D
OUT
to the next stage having a similar integrated circuit configuration via an external output electrode
4
for cascade connection.
The N-bit latch circuit portion
5
latches one row of data (Q
1
, Q
2
, . . . , Q
N
) converted into a serial form by the shift register circuit portion
3
. The level shift circuit portion
6
increases the output signals appearing at the individual stages of the latch circuit portion
5
from a logic voltage level of a low voltage of 3 to 5 volts to a higher voltage level for driving the LCD. The driver circuit portion
7
selects LCD driving power supply voltages V
0
, V
2
, V
3
, V
5
in response to the outputs from the level shift circuit portion
6
in a 1:1 relation, shapes clock pulses M applied to an electrode
9
into AC driving waveform, and sends voltages Y
1
-Y
N
to output electrodes
8
1
-
8
N
. In this integrated circuit, every stage has an identical in circuit configuration. The output electrodes, or pads,
8
1
-
8
N
correspond to the stages in a 1:1 relationship. Since the N-bit shift register circuit portion
3
and the N-bit latch circuit portion
5
are driven by the low voltage V
CC
of the power supply voltage of 3 to 5 volts applied to an electrode
10
, these stages a low voltage portion, L.V. On the other hand, a liquid crystal display requires liquid crystal driving voltages V
0
(e.g., about 38 V), V
2
(e.g., about 36 V), V
3
(e.g., about 2 V), and V
5
(e.g., about 0 V) be applied to the N-bit driver circuit portion
7
via electrodes
11
,
12
,
13
,
14
, respectively. Also, a high power supply voltage V
H
of about 40 V is applied to an electrode
15
which is connected with the level shift circuit portion
6
and also with the driver circuit portion
7
. Therefore, the level shift circuit portion
6
and the driver circuit portion
7
form a high voltage portion, H.V.
Each one stage
3
i
of the shift register circuit portion
3
, each one stage
5
i
of the latch circuit portion
5
, each one stage
6
i
of the shift level circuit portion
6
, and each one stage
7
of the driver circuit portion
7
together form a cell. Each cell, consisting of shift register
3
i
, latch circuit
5
i
and driver circuit
7
i
, and the corresponding output electrode
8
i
are referred to hereinafter as a pair. A general chip layout of such pairs is shown in
FIG. 10
, where all the stages are arranged in a parallel array forming semiconductor chip
18
. In this figure, the zigzag portions indicated by the solid lines indicate the positions at which conductive leads intersect with each other. As a whole, the cells and the electrodes are arranged symmetrically with respect to the central line of the chip extending in the X-direction. Specifically, the chip cell array is divided into a first block
16
and a second block
17
. The stages
3
1
-
3
N
of the shift register circuit portion are formed in the center of the chip. The stages
7
1
-
7
N
of the driver circuit portion are formed on the outer fringe of the chip
18
, or along the longer sides. The output electrodes
8
1
-
8
N
are arranged on the outer side of the stages
7
1
-
7
N
of the driver portion on the outer fringe of the chip. A conductive lead for a high voltage V
H
and conductive leads for liquid crystal driving power supply voltages V
0
, V
2
, V
3
, V
5
extend from the pads across the first block
16
on the driver circuit portion
7
and on the level shift circuit portion
6
in the X-direction, extend in the direction opposite to the Y-direction, and then extend across the second block
17
in the direction opposite to the X-direction. A conductive lead for the low power supply voltage V
CC
extends from the corresponding pad across the first block
16
on the latch circuit portion
5
and on the shift register circuit portion
3
in the X-direction, extends in the direction opposite to the Y-direction, and extends across the second block
17
in the direction opposite to the X-direction.
The chip
18
of the LCD driving semiconductor integrated circuit of this layout is installed, for example, on a tape carrier or film by TAB (tape automated bonding). As shown in
FIG. 11
, the chip
18
can be directly installed on a liquid crystal panel. This is known as COG (chip on glass) techniques. In particular, the liquid crystal panel comprises a lower glass substrate G
1
, an upper glass substrate G
2
, a spacer
19
that maintains a spacing between the two substrates, and a liquid-crystalline material LC which occupies the space between the two glass substrates. Transparent row electrodes
20
and transparent column electrodes
21
are formed on the substrate. As shown in
FIG. 11B
, the chip
18
is directly bonded to the flat surface of a marginal region
22
of the glass substrate which forms a non-display region by the COG techniques. Bumps
24
are deposited on the electrodes, or pads, of the chip
18
. The bumps
24
are bonded to the transparent row electrodes
20
or to the transparent column electrodes
21
, for example, by thermocompression bonding or solder bonding to effect outer lead bonding. Conductive leads
23
extending to the fringe of the marginal region
22
form terminals for connection with a printed-wiring board (not shown).
In the chip
18
, whose power supply leads are configured as described above, the leads for the power supply voltages V
H
, V
0
, V
2
, V
3
, V
5
, V
CC
and a lead for grounding (GND) extend from the electrodes, or pads, formed in the marginal region of the chip, draw a U-shaped configuration or an open loop, as shown in
FIG. 10
, and terminate at the final stages
3
N
,
5
N
,
6
N
,
7
N
of the second block. The voltages at the final stages of the second block tend to vary or be different from those voltages applied to the vicinities of the pads. This is due to the increased the lead lengths which translate to increased impedances of leads when approaching the final stages. In such a case, the lengths of the leads for the liquid crystal power supply, for example, are in excess of 10 mm. Even if the conductive leads are made of a metal, their resistance are generally tens of ohms. Fluctuations or variations in the power supply voltage applied to the final stages, as compared to the earlier stages, tend to cause a nonuniformity of the contrast of the liquid crystal display. Although it is possible to connect the leads at the final stages with the leads at the first stages so as to form a full loop without interrupting the power supply leads at the final stages by the multilayer i
Crane Sara
Seiko Epson Corporation
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