Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-08-17
2002-06-25
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S291000, C438S525000, C438S528000
Reexamination Certificate
active
06410393
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor devices comprising metal-oxide-semiconductor (MOS) transistors. The present invention has particular applicability in manufacturing highly integrated semiconductor devices with sub-micron features, high speed integrated circuitry and high reliability.
BACKGROUND ART
The escalating requirements for high performance and density associated with ultra large scale integration semiconductor devices require high speed and reliability and increased manufacturing throughput for competitiveness. As gate lengths are reduced into the deep sub-micron range, problems such as short channel effects are encountered. For example, “hot carrier injection” arises when device dimensions are reduced but the supply voltage is maintained, thereby increasing the electric field generated in the silicon substrate. Such an increased electric field enables electrons in the channel region to gain sufficient energy to be injected onto the gate dielectric, thereby degrading device performance. In addition, “punch through” arises when the drain voltage reaches a sufficiently large value, and the depletion layer associated with the drain spreads across the substrate and reaches the source, thereby enabling the charge carriers in the drain to punch through to the substrate.
A conventional approach in attempting to control or eliminate the “latch up” problem comprises forming a retrograde well structure implemented by ion implanting impurities of a conductivity type, opposite to that of the type of transistor, into the channel region with an attendant impurity concentration peak formed deep under the substrate. The impurity concentration profile of a channel region is related to the threshold voltage which normally increases with increasing impurity concentration of the channel region. Accordingly, when the impurity concentration peak is formed near the substrate surface, it is necessary to significantly increase the threshold voltage. However, when the impurity concentration peak is formed deep under the substrate surface, “latch up” would not be resolved. In addition, if the impurity concentration peak is formed deep under the substrate surface, the retrograde well does not effectively function as a potential barrier wall against noise caused by alpha particles emitted from radioactive elements in the package materials.
There exists a need for semiconductor devices having MOS transistors with reduced latch up and high reliability. There further exists a need for a method of manufacturing semiconductor devices having MOS transistors with reduced latch up and high reliability.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is a simplified. efficient and production worthy method for forming MOS transistors having improved short channel characteristics.
Another advantage of the present invention is a semiconductor device having MOS transistors with improved short channel characteristics.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following description or may be learned from the practice of the present invention. The objectives and advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising the sequential steps of: (a) providing a substrate containing an impurity of a first conductivity type; (b) forming a mask on the main surface of the substrate exposing a region in which a designated channel region of a second conductivity type, opposite the first conductivity type, MOS transistor is to be formed, the channel region having a first end proximate one source/drain region and a second end proximate the other source/drain region; (c) ion implanting an impurity at an angle to form an amorphous region in the designated channel region with a varying degree of amorphization decreasing from the first end toward the second end; (d) ion implanting an impurity of the first conductivity type into the designated channel region to form a channel implant overlapping the amorphous region; and (e) annealing to diffuse the channel implant forming a first conductivity type impurity concentration gradient across the channel region having a higher impurity concentration at the second end than at the first end.
Another aspect of the present invention is a semiconductor device comprising source/drain regions in the substrate; and a channel region, having one end approximate one of the source/drain regions and another approximate the other of the source/drain regions, containing ion implanted channel dopant impurities of the first conductivity type with an asymmetric concentration gradient increasing from one end to the other end of the channel region.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustrating the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
REFERENCES:
patent: 5223445 (1993-06-01), Fuse
patent: 5296387 (1994-03-01), Aronowitz et al.
patent: 5360749 (1994-11-01), Anjum et al.
patent: 6268640 (2001-07-01), Park et al.
patent: 2-191341 (1990-07-01), None
Hao Ming-Yin
Ishida Emi
Advanced Micro Devices , Inc.
Chaudhari Chandra
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