Semiconductor device with amorphous silicon MONOS memory...

Details Semiconductor device with amorphous silicon MONOS memory... Semiconductor device with amorphous silicon MONOS memory...

2006-12-23

2009-12-01

Rose, Kiesha L (Department: 2891)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S197000

Reexamination Certificate

active

07625796

ABSTRACT:
A semiconductor device with an amorphous silicon (a-Si) metal-oxide-nitride-oxide-semiconductor (MONOS) memory cell structure. The device includes a substrate, a dielectric layer overlying the substrate, and one or more source or drain regions embedded in the dielectric layer with a co-planar surface of n-type a-Si and the dielectric layer. Additionally, the device includes a p-i-n a-Si diode junction. The device further includes an oxide-nitride-oxide (ONO) charge trapping layer overlying the a-Si p-i-n diode junction and a metal control gate overlying the ONO layer. A method for making the a-Si MONOS memory cell structure is provided and can be repeated to expand the structure three-dimensionally.

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patent: 6890819 (2005-05-01), Wu et al.
patent: 7176064 (2007-02-01), Herner
patent: 2005/0214996 (2005-09-01), Yoshino
patent: 2006/0115939 (2006-06-01), Walker et al.
patent: 2007/0070690 (2007-03-01), Scheuerlein et al.
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