Semiconductor device with a well wherein a scaling down of...

Details Semiconductor device with a well wherein a scaling down of... Semiconductor device with a well wherein a scaling down of...

2001-09-24

2002-10-29

Ngô, Ngâ V. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S372000, C257S394000, C257S401000

Reexamination Certificate

active

06472716

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, in particular, to a semiconductor device with a well wherein a scaling down of the layout is achieved.
2. Description of the Background Art
A dynamic random access memory (hereinafter referred to as “DRAM”) will be described as an example of a conventional semiconductor device.
FIGS. 17 and 18
show a border part between a memory cell region B and a peripheral circuit region A (sense amplifiers), and a region in the vicinity thereof, in a DRAM.
As shown in
FIGS. 17 and 18
, a shallow P well
123
and a deep P well
124
are, respectively, formed in the surface of a P type semiconductor substrate
101
. A deep bottom N type well
102
is formed in a region beneath shallow P well
123
and deep P well
124
. In addition, an N well
121
is formed in the surface of P type semiconductor substrate
101
adjoining a side of shallow P well
123
.
A connection N well
122
is formed in a region between N well
121
and deep bottom N type well
102
so as to electrically connect the two. In addition, a shallow P well
120
is formed in a region on the side opposite to shallow P well
123
with N well
121
placed between them.
Shallow P well
123
and deep P well
124
are surrounded by N well
121
, deep bottom N type well
102
and connection N well
122
, and, thereby, a potential different from that of shallow P well
120
is applied thereto. In this case, a P
+
type region
130
is formed in the surface of shallow P well
120
so that a ground potential (GND) is applied to this P
+
type region
130
. Then, a P
+
type region
132
is formed in the surface of shallow P well
123
so that a potential (VBB) that is different from the ground potential is applied to this P
+
type region
132
. In addition, an N
+
type region
131
is formed in the surface of N well
121
so that a predetermined potential (VPP) that is different from the other two potentials is applied to this N
+
type region
131
.
A transistor that includes N-+ type source and drain regions
139
a
and
139
b
as well as a gate electrode part
140
is formed on the surface of deep P well
124
. This transistor is a memory cell transistor in memory cell region B.
A transistor that includes P
+
type source and drain regions
135
a
and
135
b
as well as a gate electrode part
136
is formed on the surface of N well
121
. A transistor that includes N
+
type source and drain regions
137
a
and
137
b
as well as a gate electrode part
138
is formed on surface of shallow P well
123
. These transistors are transistors in the peripheral circuit region (sense amplifiers).
Next,
FIGS. 19 and 20
show a border part between a memory cell region B and a peripheral circuit region A (word line drivers), and a region in the vicinity thereof, in a DRAM. As shown in
FIGS. 19 and 20
, a shallow P well
123
, a deep P well
124
, an N well
121
, a deep bottom N type well
102
, a connection N well
122
and a shallow P well
120
are, respectively, formed in a P type semiconductor substrate
101
in the same manner as is each well shown in FIG.
18
.
A P
+
type region
150
is formed in the surface of shallow P well
120
so that a ground potential (GND) is applied to this P
+
type region
150
. Then, a P
+
type region
152
is formed in the surface of shallow P well
123
so that a potential (VBB) which is different from the ground potential is applied to this P
+
type region
152
. In addition, an N
+
type region
151
is formed in the surface of N well
121
so that a predetermined potential (VPP) that is different from the other two potentials is applied to this N
+
type region
151
.
A transistor that includes N
−
type source and drains regions
139
a
and
139
b
as well as a gate electrode part
140
is formed on the surface of deep P well
124
. This transistor is a memory cell transistor in memory cell region B.
A transistor that includes N
+
type source and drain regions
162
a
and
162
b
as well as a gate electrode part
163
is formed on the surface of shallow P well
123
. A transistor that includes N
+
type source and drain regions
160
a
and
160
b
as well as a gate electrode part
161
is formed on the surface of shallow P well
120
. These transistors are transistors in peripheral circuit region A (word line drivers).
In this manner, in the above described DRAM, shallow P well
123
is surrounded by N well
121
, deep bottom N type well
102
and connection N well
122
and, thereby, a predetermined potential (VBB) that is different from the potentials applied to shallow P well
120
or to N well
121
is applied thereto. This predetermined potential (VBB) is applied to P
+
type regions
132
and
152
which are formed in shallow P well
123
. In addition, because deep P well
124
and shallow P well
123
are formed so as to partially overlap each other, the two are electrically connected and the potential of deep P well
123
is also fixed at predetermined potential (VBB).
On the other hand, P well
120
is fixed at the ground potential. P well
120
is formed in a region outside of the region which is surrounded by and includes N well
121
, deep bottom N type well
102
and connection N well
122
and is formed so as to adjoin a series of deep N type wells including N well
121
, connection N well
122
and deep bottom N type well
102
.
In the above described conventional DRAM, however, the following problems arise.
As described above, in order to apply a predetermined potential (VBB) to shallow P well
123
and to deep P well
124
, P
+
type regions
132
and
152
are formed in shallow P well
123
for the application of that potential. Therefore, it is necessary to secure a region for forming these P
+
type regions
132
and
152
in shallow P well
123
.
In addition, at the time when forming these P
+
type regions
132
and
152
, it is necessary to secure predetermined spaces between the N
+
type source and drain regions
132
a,
162
a of the transistor, located in the vicinity thereof, and P
+
type region
132
. Then, it is necessary to secure a predetermined space between N well
121
located in the vicinity of P
+
type region
132
and P
+
type region
132
itself.
As a result, there is a limit to the scaling down of the area occupied by shallow P well
123
in P type semiconductor substrate
101
and this has become one factor that hampers the scaling down of the layout of a DRAM.
In addition, as described above, P well
120
is formed so as to adjoin a series of deep N type wells including N well
121
, connection N well
122
and deep bottom N type well
102
. Deep bottom N well
102
and connection N well
122
are formed by injecting ions of a predetermined conductive type, such as phosphorous, into P type semiconductor substrate
101
. At this time, dispersion of the location where the well is formed occurs in the case of a comparatively deep well due to the relationship between the dispersion of the direction of ion injection and the depth of the well. Therefore, in order to maintain electrical insulation, it is necessary to secure a predetermined distance, space X, between P
+
type region
130
formed in shallow P well
120
and the adjoining series of N wells (or the end part of shallow P well
120
).
As a result, there is a limit to the reduction of space X between P
+
type region
130
and the series of N wells and this has become another factor that hampers the scaling down of the layout of a DRAM.
SUMMARY OF THE INVENTION
The present invention is provided in order to solve the above described problems and has the purpose of providing a semiconductor device wherein a scaling down of the layout can be easily achieved.
One semiconductor device according to the present invention includes a semiconductor substrate of a first conductive type that has a main surface, a first well region of the first conductive typ

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