Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-09
2003-02-04
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S585000, C438S587000, C438S588000
Reexamination Certificate
active
06514824
ABSTRACT:
BACKGROUND
The present invention relates generally to semiconductor devices and, in particular, to devices with a pair of transistors having dual work function gate electrodes.
Various electronic devices, including digital-to-analog converters, operational amplifiers, and instrumentation amplifiers, require an accurate and stable voltage source to function properly. In particular, the voltage sources should be insensitive to changes in the ambient environment, such as changes in supply voltage or temperature.
Various techniques are known for providing a reference voltage source. In theory, a reference voltage can be generated using a pair of field-effect transistors (FETs) which are identical except for their gate electrode work functions. The different work functions results in corresponding different threshold voltages which can be used to provide the reference voltage.
FIG. 1
shows a simplified circuit, consisting of two metal-oxide-semiconductor (MOS) transistors T
1
and T
2
operating in the saturation region. The transistors T
1
, T
2
are identical except for the values of their respective threshold voltages, which are achieved by providing the polysilicon gate electrodes of the transistors with different doping types. In other words, the gate electrode of one transistor, for example, the transistor T
1
, has a n-type conductivity, and the gate electrode of the second transistor T
2
has a p-type conductivity. The threshold voltage of a MOS transistor can be expressed as
V
T
=
V
FB
+
2
_ϕ
P
_
+
2
ε
s
N
d
2
(
ϕ
p
)
C
ox
,
where V
FB
is the flat band voltage of the MOS structure, &phgr;
P
is the bulk potential, N
d
is the concentration of dopants in the channel, and C
ox
is the gate capacitance per unit area. The flat band voltage V
FB
is determined by the work function difference &phgr;
MS
between the gate material and semiconductor material in the channel region, and also by the charge residing at the interface states and within the gate oxide. The work function difference &phgr;
MS
corresponds to the difference between polysilicon and bulk Fermi levels. A polysilicon layer, used as the gate electrode, is heavily doped and, therefore, the Fermi level is effectively pinned at the conduction or valence band edges for N+ and P+ type polysilicon, respectively.
If the two transistors T
1
, T
2
are formed using the same process flow such that the only difference between them is the polysilicon doping, the threshold voltage difference, V
T1
−V
T2
, would be identical to the work function difference between the bulk silicon, and N+ poly and P+ poly, respectively. In such a situation, the work function difference &phgr;
MS
of the N+ oxide-silicon and P+ oxide-silicon systems would differ by the value of the energy band gap of silicon (approximately 1.11 eV at room temperature). Accordingly, the threshold voltage difference also would be close to that value, regardless of the channel doping, gate oxide thickness and interface properties.
As shown in
FIG. 1
, drain D of each transistor is electrically coupled to its respective gate G. Thus, for each transistor T
1
, T
2
, the gate-to-source voltage V
GS
equals the drain-to-source voltage V
DS
. Therefore, both transistors operate in the saturation regime, and their drain currents can be expressed as
I
DS
=
β
2
(
V
GS
-
V
T
)
2
where
β
=
W
L
C
ox
μ
;
W, L are the gate width and length respectively, &mgr; is the carrier mobility in the channel, and C
ox
is the capacitance of gate oxide per unit area. Transistors such as those shown in
FIG. 1
which are substantially identical except for the value of their respective threshold voltages are sometimes referred to as &bgr;-identical transistors.
Also, in the circuit shown in
FIG. 1
, the drain currents I
D1
, I
D2
of the transistors T
1
, T
2
are substantially identical. Substantially identical drain currents can be achieved by using a current mirror in the drain of each transistor. The difference in the respective drain-to-source voltages &Dgr;V
DS
(=V
DS1
−V
DS2
) equals the difference in threshold voltages V
T1
−V
T2
. The voltage difference &Dgr;V
DS
is not dependent on the drain current or the supply voltage. The temperature dependence of &Dgr;V
DS
is controlled primarily by the temperature dependence of the silicon band gap, which is approximately 0.3 mV/K. Thus, the voltage difference &Dgr;V
DS
can be used as a relatively stable voltage source.
Various devices have been proposed using pairs of FETs to generate a reference voltage source. However, many of the proposed devices are difficult to implement using standard CMOS technology and fabrication flow processes. Moreover, in some designs for a reference voltage with a pair of &bgr;-identical transistors, at least a portion of one of the polysilicon gates above the channel region of the transistor has a different conductivity type than a central portion of the gate. As a result, the central portion of the transistor gate is shorter than the channel length of the transistor. Such a design effectively results in two additional transistors in series with the central transistor which can lead to the output reference voltage being dependent on the drain current.
SUMMARY
In general, techniques are described for fabricating a pair of transistors which more closely approximate ideal &bgr;-identical transistors, in other words, a pair of transistors whose dimensions and electrical characteristics, other than their respective gate electrode work functions, are substantially similar. The techniques described in greater detail below can be incorporated into a standard CMOS process and can help avoid some of the problems discussed above. The techniques, however, are not limited to the formation of precisely &bgr;-identical transistors or to the use of CMOS processes.
In one particular aspect, a semiconductor device includes a substrate of a first conductivity type and a pair of field effect transistors formed in the substrate. Each transistor includes source and drain regions of a second conductivity type opposite the first conductivity type and a channel region. An area extending from the source region to the drain region defines a length of the channel. Each transistor also includes a gate electrode disposed above the channel region. The gate electrode of a first one of the transistors is of the second conductivity type. A portion of the gate electrode of the second one of the transistors is of the first conductivity type and extends above the entire length of the channel of the second transistor. The lengths of the channels of the first and second transistors are substantially the same.
In another aspect, a semiconductor device includes a substrate of a first conductivity type and a pair of field effect transistors formed in the substrate. Each transistor includes source and drain regions of a second conductivity type opposite the first conductivity type and a channel region. An area extending from the source region to the drain region defines a length of the channel. Each transistor also includes a gate electrode disposed above the channel region and a field oxide region disposed between the gate electrode and the channel region. The gate electrode of a first one of the transistors has a first work function and includes dopants only of the first type of conductivity. The gate electrode of the second one of the transistors has a second work function and includes dopants only of the second type of conductivity. The lengths of the channels of the first and second transistors are substantially the same.
Such devices can be used to form, for example, a reference voltage source and can be incorporated into digital-to-analog converters, operational amplifiers, instrumentation amplifiers, and other electronic devices requiring an accurate and stable voltage source.
Techniques for fabricating such devices also are described below.
Some implementations include one or more of th
Kolnik Jan
Randazzo Todd A.
Carstens Yee & Cahoon LLP
LSI Logic Corporation
Vockrodt Jeff
Zarabian Amir
LandOfFree
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