Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-07-20
2001-02-13
Hardy, David (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000, C257S412000, C257S413000, C257S414000, C257S773000
Reexamination Certificate
active
06188115
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to a semiconductor device having a conductive layer of small conductive resistance.
2. Description of the Prior Art
Among semiconductor devices, nonvolatile semiconductor memory devices losing no data in power-off states are widely employed in general. An EEPROM (electrically erasable and programmable read only memory) which can freely program data and is capable of electrically writing and erasing information is known as one of such nonvolatile semiconductor memory devices.
In relation to such an EEPROM, known is a flash memory having memory cells each formed by a single transistor, which can electrically batch-erase information charges written therein.
FIG. 34
is a sectional view showing a conventional flash memory. Referring to
FIG. 34
, a source region
113
and drain regions
102
are formed on a surface of a silicon substrate
101
at distances from each other. Floating gate electrodes
104
are formed on the silicon substrate
101
through gate oxide films
103
. Control gate electrodes
106
consisting of doped polysilicon layers
106
a
and tungsten silicide layers
106
b
are formed on the floating gate electrodes
104
through interlayer isolation films
105
. Side wall oxide films
107
are formed on side walls of the control gate electrodes
106
and the floating gate electrodes
104
. A silicon oxide film
115
is formed on the silicon substrate
101
, to cover the control gate electrodes
106
.
When gate electrodes are refined, conductive resistance thereof is disadvantageously increased in general. Known is a method of preventing this problem by forming wiring layers on the gate electrodes and connecting the former with the latter thereby reducing conductive resistance.
FIG. 35
is a sectional view showing wiring layers
294
formed on conventional gate electrodes
292
. Referring to
FIG. 35
, the gate electrodes
292
consisting of doped polysilicon layers
292
a
and tungsten silicide layers
292
b
are formed on a silicon substrate
201
through gate oxide films
291
. A silicon oxide film
293
is formed to cover the gate electrodes
292
. The wiring layers
294
of aluminum are formed on the silicon oxide film
293
in a width substantially identical to that of the gate electrode
292
. The wiring layers
294
are electrically connected with the gate electrodes
292
respectively.
In this structure, the sectional areas of conductive layers are not reduced following refinement of the gate electrodes
292
, due to the presence of the wiring layers
294
. Consequently, increase of the conductive resistance can be prevented.
When the conventional flash memory shown in
FIG. 34
is further refined, the sectional area of the source region
113
is reduced. Thus, the conductive resistance of the source region
113
is increased, to retard the operating speed of the flash memory. Further, a leakage current is readily generated. In order to solve this problem, a wiring layer of aluminum or the like may be formed on the silicon oxide film
115
, to be electrically connected with the source region
113
. In this method, however, the wiring layer formed on the silicon oxide film
115
causes a step, to result in a problem such as difference in depth of focus in a subsequent photolithographic step, for example.
When the conventional semiconductor device shown in
FIG. 35
is further refined, on the other hand, the sectional areas of the wiring layers
294
are reduced to increase the conductive resistance. The wiring layers
294
may be increased in height, in order to increase the sectional areas. In this case, however, it is so difficult to pattern the wiring layers
294
in prescribed shapes that adjacent ones of the wiring layers
294
readily come into contact with each other. Consequently, the yield of the semiconductor device is disadvantageously reduced.
SUMMARY OF THE INVENTION
The present invention has been proposed in order to solve the aforementioned problems, and an object thereof is to provide a semiconductor device having a conductive layer of small conductive resistance and including only a small step.
Another object of the present invention is to provide a semiconductor device having a fine wiring layer of small conductive resistance.
A semiconductor device according to an aspect of the present invention comprises a semiconductor substrate, a first conductive layer and an interlayer isolation film. The semiconductor substrate has a major surface. The first conductive layer is formed on a portion of the major surface of the semiconductor substrate to extend in one direction. The interlayer isolation film is formed on the major surface of the semiconductor substrate, and has a trench reaching the first conductive layer. The trench is defined by opposite side walls of the interlayer isolation film, and extends in one direction along the conductive layer. The semiconductor device further comprises a second conductive layer which is formed on opposite side walls of the trench. A part of the second conductive layer is in contact with a partial surface of the first conductive layer while exposing another partial surface of the first conductive layer.
In the semiconductor device having the aforementioned structure, the second conductive layer is in contact with the first conductive layer, thereby increasing the sectional areas of the conductive layers. Thus, a semiconductor device having small conductive resistance can be provided. Further, the second conductive layer is formed on the side walls of the trench, not to project upward beyond the interlayer isolation film. Thus, a semiconductor device having only a small step can be provided. In addition, the first conductive layer is partially exposed, to include a part which is not in contact with the second conductive layer in its surface. When the first conductive layer is formed by an impurity region, therefore, the second conductive layer hardly absorbs the impurity contained in the first conductive layer. Consequently, the first conductive layer can be suppressed from increase of conductive resistance, thereby preventing generation of a leakage current.
The semiconductor device preferably further comprises an electrode layer which is formed on the major surface of the semiconductor substrate to extend along the first conductive layer.
Further, it is preferable that the semiconductor substrate has a concave part communicating with the trench, the concave part is defined by a side wall of the first conductive layer, and the second conductive layer is formed on the side walls of the trench and the concave part to be in contact with the first conductive layer. In this case, the sectional area of the second conductive layer is increased due to the formation on the side wall of the concave part. Thus, the resistance of the conductive layers is further reduced.
Further, it is preferable that the first and second conductive layers are source lines.
A semiconductor device according to another aspect of the present invention comprises a semiconductor substrate, an electrode layer, a first conductive layer, a side wall insulator film, and a second conductive layer. The semiconductor substrate has a major surface. The electrode layer is formed on the major surface of the semiconductor substrate to extend in one direction, and has a side wall. The first conductive layer is formed on a portion of the major surface of the semiconductor substrate to extend along the electrode layer. The side wall insulator film is formed on the side wall of the electrode layer. The second conductive layer is formed on the side wall insulator film. A part of the second conductive layer is in contact with a partial surface of the first conductive layer while exposing another partial surface of the first conductive layer.
In the semiconductor device having the aforementioned structure, the second conductive layer is in contact with the first conductive layer, thereby increasing the sectional area
Hardy David
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Ortiz Elgardo
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