Register transfer level power optimization with emphasis on...

Details Register transfer level power optimization with emphasis on... Register transfer level power optimization with emphasis on...

1998-06-01

2001-11-27

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06324679

ABSTRACT:

IA. FIELD OF THE INVENTION
This invention relates to reduction of power consumption for digital VLSI sequential circuits. Specifically, this invention relates to a system and method for reducing power consumption by reducing glitches. This invention is embodied in a system and in methods for reducing power consumption in a sequential circuit by reducing glitches.
IB. BACKGROUND OF THE INVENTION
Reducing power consumption in VLSI circuits has become important for several reasons. Mobile or portable electronic devices, which already account for a significant portion of all consumer electronics sold, are battery driven. Reducing power consumption in the various components of such systems prolongs the life of the batteries, which is highly desirable. Excessive power consumption also leads to an increase in chip packaging and cooling costs, which increase the total system cost. Another benefit of reduced power consumption is increased reliability of VLSI circuits. Reducing average power consumption or peak power consumption have their own merits. For example, reducing average power consumption increases battery life, while reducing peak power consumption reduces packaging and cooling costs. This invention seeks to minimize average power consumption.
Most savings in power consumption can be obtained through a combination of several techniques applied at different levels of the design hierarchy. Several design and synthesis techniques have been proposed for power optimization at the technology. See A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, “Low-power CMOS digital design,”
IEEE J. Solid-State Circuits
, pp. 473-484 (April 1992).
Such techniques have been applied to the transistor level. See S. Devadas and S. Malik, “A survey of optimization techniques targeting low power VLSI circuits,” in
Proc. Design Automation Conf
., pp. 242-247 (June 1995). Physical level of a sequential circuit design is another area where such techniques have been applied. See H. Vaishnav and M. Pedram, “PCUBE: A performance driven placement algorithm for low power designs,” in
Proc. European Conf. Design Automation
, pp. 72-77, (September 1993). Similarly such techniques have also been applied at the logic design level. See S. Devadas and S. Malik, “A survey of optimization techniques targeting low power VLSI circuits,” in
Proc. Design Automation Conf
., pp. 242-247 (June 1995).
On the architectural power estimation front, a method based on a uniform white noise model of signal statistics was presented in S. R. Powell and P. M. Chau, “Estimating power dissipation of VLSI signal processing chips: the PFA technique,” in
Proc. VLSI Signal Processing IV
, pp. 250-259 (1990). A more accurate estimation method based on a dual-bit-type model was presented in P. E. Landman and J. M. Rabaey, “Power estimation for high level synthesis,” in
Proc. European Conf. Design Automation
, pp. 361-366 (February 1993) and P. E. Landman and J. M. Rabaey, “Black-box capacitance models for architectural power analysis,” in
Proc. Int. Vlkshp. Low Power Design
, pp. 165-170 (April 1994). The use of entropy as a measure of average switching activity, and its use in high-level power estimation was suggested in D. Marculescu, R. Marculescu, and M. Pedram, “Information theoretic measures for energy consumption at the register-transfer level,” in
Proc. Int. Symp. Low Power Design
, pp. 81-86 (April 1995) and F. N. Najm, “Towards a high-level power estimation capability,” in
Proc. Int. Synp. Low Power Design
, pp. 87-92 (April 1995) . Early work in architectural power optimization was presented in A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, “Low-power CMOS digital design,”
IEEE J. Solid-State Circuits
, pp. 473-484 (April 1992) and A. P. Chandrakasan, M. Potionjak, R. Mehra, J. Rabaey, and R. Brodersen, “Optimizing power using transformations,”
IEEE Trans. Computer-Aided Design
, vol. 14, pp. 12-31 (January 1995). In A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, “Low-power CMOS digital design,”
IEEE J. Solid-State Circuits
, pp. 473-484 (April 1992) the use of architectural parallelism was proposed based on data path replication and pipelining to enable supply voltage scaling for power reduction. A methodology that used a variety of architectural transformations to reduce power consumption was presented in A. P. Chandrakasan, M. Potionjak, R. Mehra, J. Rabaey, and R. Brodersen, “Optimizing power using transformations,”
IEEE Trans. Computer-Aided Design
, vol. 14, pp. 12-31 (January 1995). In A. Chatterjee and R. K. Roy, “Synthesis of low power DSP circuits using activity metrics,” in
Proc.
7
th Int. Con VLSI Design
, pp. 265-270 (January 1994), switching activity metrics were used to reduce power consumption in bit-serial digital filters. Optimizing memory-dominated computations for power consumption was addressed in S. Wytack, F. Catthoor, F. Franssen, L. Nachtergaele, and H. D. Man, “Global communication and memory optimizing transformations for low power systems,” in
Proc. Int. Wkshp. Low Power Design
, pp. 203-208 (April 1994), and D. Lidsky and J. Rabaey, “Low-power design of memory intensive functions,” in
Proc. Symp. Low Power Electronics
, pp. 16-17, (October 1994). Tools for power estimation and design space exploration at the behavior level were presented in R. Mehra and J. Rabaey, “Behavioral level power estimation and exploration,” in
Proc. Int. Wkshp. Low Power Design
, pp. 197-202 (April 1994). In L. Goodby, A. Orailoglu, and P. M. Chau, “Microarchitectural synthesis of performance-constrained, low-power VLSI designs,” in
Proc. Int. Conf. Computer Design
, pp. 323-326 (October 1994), module selection and pipelining were used to combat the performance degradation that results from reducing the supply voltage. Methods for performing allocation and assignment in order to minimize switching activity and switched capacitance in the data path were presented in A. Raghunathan and N. K. Jha, “Behavioral synthesis for low power,” in
Proc. Int. Conf. Computer Design
, pp. 318-322 (October 1994), A. Raghunathan and N. K. Jha, “An ILP formulation for low power based on minimizing switched capacitance during datapath allocation,” in
Proc. Int. Symp. Circuits & Systems
, pp. 1069-1073 (May 1995), J. M. Chang and M. Pedram, “Register allocation and binding for low power,” in
Proc. Design Automation Conf
., pp. 29-35 (June 1995), and A. Dasgupta and R. Karri, “Simultaneous scheduling and binding for power minimization during microarchitecture synthesis,” in
Proc. Int. Symp. Low Power Design
, pp. 69-74 (April 1995). Techniques to reduce power consumption during high level synthesis based on reducing activity in functional units were presented in E. Musoll and J. Cortadella, “High-level synthesis techniques for reducing the activity of functional units,” in
Proc. Int. Symp. Low Power Design
, pp. 99-104 (April 1995). The use of limited-weight codes to minimize power consumption in buses and I/O circuitry was described in M. Stan and W. P. Burleson, “Limited-weight codes for low-power I/O,” in
Proc. Int. Wkshp. Low Power Design
, pp. 209-214 (April 1994). A multi-phase clocking scheme for RTL circuits that reduces activity by naturally imposing shut-off for inactive parts of the circuit was proposed in C. Papachristou, M. Spining, and M. Nourani, “A multiple clocking scheme for low power RTL design,” in
Proc. Int. Symp. Low Power Design
, pp. 27-32 (April 1995). An optimization tool for average and peak power consumption during behavioral synthesis, based on genetic search was described in R. S. Martin and J. P. Knight, “Power Profiler: Optimizing ASICs power consumption at the behavioral level,” in
Proc. Design Automation Conf
., pp. 42-47 (June 1995). Techniques for software power estimation and optimization were presented in V. Tiwari, S. Malik, and A. Wolfe, “Power analysis of embedded software: a first step towards software power minimization,” in Proc. Int. Conf. Computer-Aided Design (November 1994).
The importance of eliminating glitches in the design of digital VLSI circuits has been reco

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