Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2001-10-04
2003-06-24
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S685000, C257S686000, C257S723000, C257S773000, C257S777000, C257S778000, C257S779000, C257S786000
Reexamination Certificate
active
06583514
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor device in which an electrode on a semiconductor chip and an electrode on a substrate are electrically connected in opposition to each other, and to a method of manufacturing the same.
More specifically, this invention is directed to a bonding structure of a semiconductor device and a bonding method thereof.
In flip-chip mounting of a semiconductor device, metal bonding is generally used as a connection structure in order to obtain electrical connection.
Here, binary alloy solder including Sn and Pb or hypercomplex solder alloy containing Sn as a major component is often used in such metal bonding.
In particular, a structure referred to as “C4” (control collapse chip connection) is existing as the flip-chop mounting structure.
Referring now to
FIGS. 1A and 1B
, description will be hereinafter made about such a connection structure as a related art.
A barrier metal with excellent solder wettability, such as, Cu and Ni is used as an electrode
2
on a semiconductor chip
1
and an electrode
2
on a substrate
4
for providing the semiconductor chip
1
thereon.
With such a structure, solder
20
including Sn and Pb is supplied onto the electrode
2
by plating or sputtering, and is melted by heating, then being formed to a spherical shape on the electrode
2
.
Thus, a solder bump is formed on the substrate
4
, and a semiconductor chip
1
is positioned over the solder bump.
Subsequently, the semiconductor chip
1
is placed over the substrate
4
, is melted by heating, and is bonded by the use of the solder
20
.
In thus-obtained connection structure, Cu serving as the electrode
2
and Sn serving as the solder
20
are connected by forming intermetallic compound layers
5
a
and
5
b.
Thereby, the semiconductor chip
1
and the substrate
4
are electrically connected via the solder
20
.
Under this circumstance, the solder
20
serves to form a space between the semiconductor chip
1
and the substrate
4
, so that stress concentration, which occurs by a thermal expansion difference between the semiconductor chip
1
and the substrate
4
, will be relieved.
In case that the solder
20
serves as eutectic of SnPb, a barrier metal of Ni or CrCu/Cu is used as the electrode
2
of the semiconductor chip
1
.
Alternatively, when solder with a high-melting point of Pb 95% Sn 5% is used as the electrode
2
, a barrier metal made of Cu will be used.
By adopting such C4 connection, the connection can be carried out only by heating without the load for the electrode
2
or the semiconductor chip
1
. With this advantage, the C4 connection will be suitable for mounting an area array semiconductor chip in which electrodes are arranged on a circuit surface.
Further, another suggestion has been made about a contact bonding (solderless) technique of an Au bump using an Au stud bump as the connecting structure for realizing the electrical connection of the flip-chip mounting.
Referring to
FIGS. 2A and 2B
, description will be made about such a contact bonding technique as another related art.
An Au stud bump
23
is formed on an electrode
24
of a semiconductor chip
1
by the use of Au wire bonding. Further, an electrode
2
of an opposed substrate
4
, on which the semiconductor chip
1
will be arranged, is covered with an Au plate
22
. In this condition, the Au stud bump
23
and the Au plate
22
are connected to each other by heating and pressing.
Due to this bonding technique, a normally-used Al electrode can be used as the electrode
24
of the semiconductor chip
1
. Further, Au is excessively resistant to oxidation. Consequently, the connection can be simply performed by heating and pressing.
However, the above-described connection due to C4 illustrated in
FIGS. 1A and 1B
is inferior to reliability in keeping under a high temperature or a moisture cycle.
When the eutectic solder is used and Cu is used as the electrode, the electrode of the semiconductor chip is melted or dissolved by the solder by repeatedly heating during assembling or mounting a package. In consequence, adhesion with a base film (an underlying layer) of the electrode will be degraded.
Moreover, the normally-used Al can not be employed as the electrode. Thereby, the electrode having a specific specification becomes necessary, resulting in high cost.
In addition, even when the C4 connection using the eutectic solder is carried out by the use of the barrier metal having the specific specification under used environment of high temperature, the intermetallic compound layer is formed by a solid phase diffusion reaction between the barrier metal and Sn.
Under this circumstance, Sn constituting the solder near the interface and Sn, which is dissolved or melted into Pb, diffuses, so that segregation of Pb takes place near the intermetallic compound layer.
Thus, the intermetallic compound layer and the segregated Pb layer excessively different in mechanical characteristic cause to occur destroy in stress concentration due to the temperature cycle.
On the other hand, the normally-used Al electrode can be employed in such contact bonding using the Au stud bump illustrated in
FIGS. 2A and 2B
. However, a load or a supersonic wave is used together during forming the Au stud bump, resulting in large impact.
Moreover, the similar structure can be formed by the use of the Au plate. However, the bonding must be carried out by applying a high load under an excessively high temperature within the range 300° C. between 400° C. during bonding so as to cause plastic deformation for the bonding surface and to form a sufficient adhesion surface.
Accordingly, the semiconductor chip may be destroyed or otherwise may be varied in characteristics for the area array semiconductor chip having the electrode on the semiconductor chip (particularly, on the circuit surface), thereby making it difficult to adopt the above-mentioned bonding technique.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide a semiconductor device having a stable bonding structure without defects on the condition that reliability is not degraded by high temperature keeping or a temperature cycle in a bonding structure of a semiconductor chip.
It is another object of this invention to provide a method of manufacturing semiconductor device having a stable bonding structure without defects under a low load and a low heating temperature under such a condition that reliability is not degraded by high temperature keeping or a temperature cycle in a bonding structure of a semiconductor chip.
A semiconductor device according to this invention includes a semiconductor chip. With this structure, a substrate is arranged in opposition to the semiconductor chip. A first electrode is placed on the semiconductor chip while a second electrode is placed on the substrate.
Further, an intermetallic compound layer is arranged between the first electrode and the second electrode.
In this event, each of the first and second electrodes is made of predetermined electrode material. The intermetallic compound layer is made of the electrode material and bonding material supplied to at least one of the first and second electrodes.
Here, each of the first and second electrodes preferably has the same shape. For example, the shape may be a convex shape.
The first and second electrodes may be different to each other in dimension. For example, either one of the first and second electrodes has a concave shape while the other one has a convex shape.
The first electrode may be protruded from a surface of the semiconductor chip, and the bonding material is supplied on the first electrode so as to entirely cover the first electrode.
Alternatively, the first electrode is protruded from a surface of the semiconductor chip, and the bonding material is supplied on a top surface of the first electrode.
The bonding material may be supplied to a region having an opening area smaller than an area of either one of the first and second electrodes.
Herein, the substrate may be replaced by another semiconductor ch
Tago Masamoto
Takahashi Kenji
Tomita Yoshihiro
Soward Ida M.
Young & Thompson
Zarabian Amir
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