Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2000-03-24
2002-10-08
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S151000, C438S257000, C438S261000, C438S771000, C438S765000
Reexamination Certificate
active
06461984
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to a semiconductor memory device, particularly to an electrically erasable/programmable read only memory (hereinafter, referred to as “EEPROM”) or flash memory using N
2
O plasma oxide film as a tunnel oxide and an interpoly dielectric and a method of fabricating of the polysilicon thin film transistor with a high breakdown voltage and higher charge to breakdown characteristics to provide high-density flash memory or EEPROM.
BACKGROUND OF THE INVENTION
Generally, high-density flash memories or EEPROMs are nonvolatile memory devices operated depending on a difference between threshold voltages when electrons are injected and ejected from a silicon substrate into a floating gate via a gate oxide film or a tunnel oxide film.
Such high-density flash memory or EEPROM has been mainly used for the memory device of digital camera or personal computer. Thus, it is important to reduce the size of the memory cell in order to meet its cost performance.
The flash memory with the capacity of 1GB or more by the existing technology by which cell arrays and peripheral devices are disposed on the single crystalline silicon can be produced by a lithography process using ArF light source with a wavelength of 193 nm and a shallow trench isolation process having its isolation space of 0.25 &mgr;m or less, and it evitably increases the cost of memory device.
Such problems can be solved by using the polysilicon thin film transistor to form cell arrays, which provides high-density flash memory or EEPROM without increasing the cost.
Conventionally, since the polysilicon thin film transistor is formed of a mesa structure, it has advantages of small isolation space, ease fabricating process, fast operating speed because of reduced junction capacitance of only 10% as compared to the existing cell arrays, etc..
However, the flash memory or EEPROM which adopts the polysilicon thin film transistor using thermal oxide film or high temperature oxide (HTO) formed by conventional method as a gate oxide film have poor leakage current and low breakdown voltage characteristics, compared to the thermal oxide film formed on the crystalline silicon as shown in FIG.
2
.
Thus, it is necessary that the thin oxide film formed on the polysilicon has a high breakdown voltage and a high charge to breakdown characteristics in order to fabricate high-density flash memory or EEPROM using polysilicon thin film transistor.
Additionally, when the polysilicon thin film transistor is used as the switching device in an active matrix liquid crystal display, it is necessary to provide higher electron and hole mobilities, the excellent polyoxide and lower leakage current characteristics.
In order to achieve such characteristics, the roughness between the polysilicon and the polyoxide should be minimized and defects in the polysilicon thin film should also be eliminated. In other words, it is possible to produce a high performance polysilicon thin film transistor by providing the excellent gate oxide film.
A method which adopts the plasma process under O
2
ambient environment has been proposed to form the oxide film on the polysilicon substrate.
However, since this method has an extremely high growth rate, it is difficult to form the thinner oxide film.
Also, in the memory device, at the time of write or erase operation of informations, the number of electrons introduced into the floating gate should be kept constantly. However, when the film quality of the dielectric interposed between the floating gate and the control gate is deteriorated, its leakage current increases and the number of electrons being introduced thereto decreases.
As a result, the threshold voltage fluctuates, leading to an errornously operation in the memory device.
Therefore, for the high quality memory cell, it is necessary to improve the dielectric.
As has been explained, since the leakage current characteristics of the high-density flash memory or EEPROM provided with the thermal oxide film formed on the polysilicon is inferior to that of the thermal oxide film formed on the single crystalline silicon, the tripple layer structure comprised of an oxide
itride/oxide has been used to improve the characteristics of interpoly dielectric.
However, the triple layer dielectric is very complex in its structure and is difficult to form the overall oxide film to have thickness of 13 nm. Further, since process to form the triple-layered structure should be performed at the high temperature of about 900° C., gate oxide can be deteriorated because of the stress of the nitride. Also, it is necessary for an expensive equipments for manufacturing this device, resulting in increase of its manufacturing cost.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a highly reliable thin film transistor with N
2
O plasma oxide having an excellent leakage current characteristics comparable to the thermal oxide film formed on the crystalline silicon.
Another object of the present invention is to provide a method of fabricating EEPROM or flash memory using N
2
O plasma oxide as a tunnel oxide.
Another object of the present invention is to provide an electrically erasable/programmable read only memory(EEPROM) and flash memory using N
2
O plasma oxide film as an interpoly dielectric between the floating gate and the control gate.
Still another object of the present invention is to provide a single layer N
2
O plasma oxide film in place of said triple layer structure.
Still another object of the present invention is to provide a highly reliable interpoly dielectric with a tripple layer structure comprised of: N
2
O plasma oxide in 1st layer—nitride in 2nd layer formed using a LPCVD under SiH
4
environment—oxide in 3th layer using thermal oxidation process under N
2
O environment.
REFERENCES:
patent: 5498577 (1996-03-01), Fulford, Jr. et al.
patent: 5587330 (1996-12-01), Yamazaki
patent: 5591681 (1997-01-01), Wristers et al.
patent: 405243577 (1993-09-01), None
patent: 407106593 (1995-04-01), None
Han Chui-Hi
Hur Sung-Hoi
Lee Jin-Woo
Lee Nae-In
Bachman & LaPointe P.C.
Brophy Jamie L.
Jr. Carl Whitehead
Korea Advanced Institute of Science & Technology
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