Electronic digital logic circuitry – With test facilitating feature
Reexamination Certificate
2000-01-07
2002-07-30
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
With test facilitating feature
C326S101000
Reexamination Certificate
active
06426645
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device that fixes a potential on an input signal wiring, that is connected to either an input terminal or an input/output terminal, by a pull-up or a pull-down.
2. Description of Related Art
As the number of pins increases, semiconductor devices of the type described above do not retain an input signal wiring, that is connected to an input terminal or an input/output terminal, in a floating state, but fix it at a potential “H” by a pull-up or at a potential “L” by a pull-down. This is because, unless potentials on all input signal wirings are controlled immediately after the power is turned on, the potentials do not stabilize if the input signal wirings are in a floating state, and the control therefor is very complex when many pins are present.
Before shipping out semiconductor devices, a semiconductor manufacturer must conduct input leak tests to measure whether potentials on the input signal wirings, that are connected to input terminals or input/output terminals, leak to the power source voltage VDD side or to the ground voltage VSS side.
A proposed technology that enables the input leak test is described in Japanese Laid-open Patent Application HEI 4-213849. Prior art technology 1 described in the publication will be described below with reference to FIG.
7
.
Referring to
FIG. 7
, a semiconductor device includes a test terminal
10
and a plurality of input terminals
20
,
30
. The test terminal
10
connects to a control circuit
12
. The control circuits
12
has output wirings that define an inversion signal wiring
14
and a non-inversion signal wiring
16
.
The input terminals
20
and
30
are connected through input signal wirings
22
and
32
to input circuits
24
and
34
, respectively. The input signal wiring
22
is grounded through a pull-down MIS (metal-insulation-silicon) transistor, for example, a N-type MOS (metal-oxide-silicon) transistor
26
. The transistor
26
has a gate that is connected to the inversion signal wiring
14
. Power source voltage VDD is applied to the input signal wiring
32
through a pull-up MIS transistor, for example a P-type MOS transistor
36
. The transistor
36
has a gate that is connected to the non-inversion signal wiring
16
.
Therefore, during normal operation, when a signal at level “L” is applied to the test terminal
10
, the inversion signal wiring
14
of the control circuit
12
attains logic level “H”, the N-type MOS transistor
26
turns on, and the input signal wiring
22
has a potential fixed at level “L”. On the other hand, the non-inversion signal wiring
16
of the control circuit
12
attains logic level “L”, the P-type MOS transistor
36
turns on, and the input signal wiring
32
has a potential fixed at level “H”.
During an input leak test, a signal at a potential level “H” is applied to the test terminal
10
. As a result, the inversion signal wiring
14
of the control circuit
12
attains logic level “L”, the N-type MOS transistor
26
turns off, and the input signal wiring
22
is placed in a floating state. On the other hand, the non-inversion signal wiring
16
of the control circuit
12
attains logic level “H”, the P-type MOS transistor
36
turns off, and the input signal wiring
32
is also placed in a floating state. In this manner, when the input signal wirings
22
and
32
are placed in a floating state, the input leak test can be correctly conducted. If a current flows during the test, it is determined that the tested semiconductor device is defective.
FIG. 8
shows a semiconductor device in which the structure shown in
FIG. 7
is applied. A test cell
40
shown in
FIG. 8
corresponds to the test terminal
10
of FIG.
7
.
As shown in
FIG. 8
, a total of n number of above-described input cells or input/output cells
50
-
1
,
50
-
2
, . . .
50
-n having input terminals
20
,
30
or input/output terminals are disposed in a peripheral circuit region extending along four edges of the semiconductor device. Accordingly, the inversion signal wirings
14
and the non-inversion signal wirings
16
connected to the test cells
40
need to be formed along generally the entire circumference of the peripheral circuit region of the semiconductor device.
However, the wiring capacitance of the inversion and non-inversion signal wirings
14
and
16
that extend such a long distance reaches several tens pF. Also, the gate capacitance of each of the pull-down or pull-up transistors
26
,
36
is several tens fF. However, when a large number of these transistors are present, their total gate capacitance reaches several tens pF. As a consequence, the control circuit
12
shown in
FIG. 7
needs to be composed of circuits having a large capacitance. Therefore, the control circuit
12
having the large capacitance occupies a large area. Moreover, the wiring capacitance of the inversion and non-inversion signal wirings
14
,
16
and the total gate capacitance of the pull-down and pull-up transistors greatly depend on the size of a chip. Accordingly, the capacitance of the control circuit
12
is required to be determined depending on the size of a chip, which is inconvenient.
When the inversion and non-inversion signal wirings
14
,
16
have a large wiring capacitance, problems of signal delays cannot be ignored. This is because, in recent years, the time for an input leak test is controlled in units of sub-seconds, and a higher operation speed is required.
Also, when the inversion and non-inversion signal wirings
14
,
16
have a large wiring capacitance, the waveform of the control signal becomes blunt. This makes it difficult to design circuits to provide logic signals to turn on or turn off the gates of the pull-down or pull-up transistors
26
,
36
that are located far from the control circuit
12
.
The inventor of the present application proposed an improved technology in Japanese Laid-open patent application HEI 7-176618 to solve the above-described prior art problems.
FIG. 9
shows the technology disclosed the above-described publication. Referring to
FIG. 9
, a test cell
40
includes a test terminal
10
, a control signal wiring
42
connected to the test terminal
10
, an N-type MOS transistor
44
that always maintains the potential on the control signal wiring
42
at level “L”, and an inverter
46
provided in the control signal wiring
42
. The control signal wiring
42
is formed along generally the entire circumference of the peripheral circuit region of the semiconductor device, as shown in FIG.
10
.
FIG. 9
also shows two input cells
50
-
1
and
50
-
2
that have substantially the same structure of those shown in FIG.
7
. Each of the two input cells
50
-
1
and
50
-
2
has a buffer
100
provided in the control signal wiring
42
. Each of the buffer
100
is formed from two serially connected inverters
100
-
1
and
100
-
2
.
The input cell
50
-
1
has a pull-down N-type MOS transistor
26
. A control signal buffered by the buffer
100
is inputted in a gate of the N-type MOS transistor
26
. On the other hand, the input cell
50
-
2
has a pull-up P-type MOS transistor
36
. A signal between the two inverters
100
-
1
and
100
-
2
that compose the buffer
100
is supplied to a gate of the P-type MOS transistor
36
.
By the structure described above, during normal operation when the potential of the test terminal
10
is at “L” level, both of the N-type and P-type MOS transistors
26
and
36
are turned on, and the potential on each of the input signal wirings
22
and
32
is fixed. During input leak test when the potential of the test terminal
10
is at “H” level, both of the N-type and P-type MOS transistors
26
and
36
are turned off, and each of the input signal wirings
22
and
32
is set in a floating state.
As shown in
FIG. 10
, the peripheral circuit region of the semiconductor device is also provided with a variety of cells other than the above-described test cells
40
, the input cells or input/output cells
50
-
1
through
50
-n having input termin
Cho James H
Hogan & Hartson L.L.P.
Seiko Epson Corporation
Tokar Michael
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