Semiconductor device tester for measuring skew between...

Details Semiconductor device tester for measuring skew between... Semiconductor device tester for measuring skew between...

1999-12-03

2003-07-01

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Skew detection correction

C714S736000, C714S744000, C324S1540PB, C327S012000

Reexamination Certificate

active

06587976

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor device testers.
RELATED APPLICATIONS
This application is related to Korean Application No. 98-53644, filed Dec. 8, 1998, the disclosure of which is hereby incorporated herein by reference.
BACKGROUND OF THE INVENTION
Various complex semiconductor devices, such as integrated circuit packages with a number of input/output pins, are commonly manufactured and utilized in a variety of areas. It is often desirable to test such devices after their manufacture to verify their performance. To facilitate testing of such integrated semiconductor devices a variety of semiconductor device tester designs have been provided. Such conventional testers typically provide for detecting transitions of output data at a specific pin during a test of a semiconductor device and further to detect a data output speed or rate for a specific pin. Generally, however, such conventional testers do not provide for a measurement of comparative data streams between different input/output pins of the semiconductor device. Accordingly, such devices typically are not able to measure the skew, or response time difference, between data output from respective data input/output pins of a semiconductor device. This limitation is becoming problematic as semiconductor device designers work to reduce such skew in light of the ever increasing speed of operations of various semiconductor devices. As the semiconductor devices migrate to ever higher operating speeds, the likelihood of errors being generated as a result of skew between output data increases.
One type of prior art semiconductor tester device attempts to use a data strobe in the semiconductor device tester. Nonetheless, a problem may still exist using this approach in that expected values generated by the tester and the actual output data from the semiconductor device being tested are generally compared only to detect transitions of output data at a point and time specified by the strobe which is not suitable for determining the skew between the output of two data input/output pins of the semiconductor device.
An example of such a prior are semiconductor device tester will now be further described with reference to the schematic block diagram of FIG.
1
. As shown in
FIG.1
, the semiconductor device
100
is electrically coupled to a tester
200
. The semiconductor device
100
includes control signal input pins and data input/output pins which are coupled to the tester
200
. The tester
200
includes a control signal input driver
10
, data input drivers
12
-
1
,
12
-
2
, . . . ,
12
-n, amplifier gates
14
-
1
,
14
-
2
, . . . ,
14
-n,
16
-
1
,
16
-
2
, . . . ,
16
-n, inverters
18
-
1
,
18
-
2
, . . . ,
18
-n, AND gates
20
-
1
,
20
-
2
, . . . ,
20
-n,
22
-
1
,
22
-
2
, . . . ,
22
-n,
26
-
1
,
26
-
2
, . . . ,
26
-n, OR gates
241
,
242
, . . . ,
24
-n, D flip flops
28
-
1
,
28
-
2
, . . . ,
28
-n, a test pattern generator circuit
30
and a timing generator circuit
32
.
The embodiment illustrated in
FIG.1
represents a tester for use where the data input/output pins of the semiconductor device
100
are common. When the data input and data output pins of the semiconductor device
100
are separate pins, it is to be understood by those of ordinary skill in the art that the data input drivers are connected to data input pins
12
while the amplifier gates
14
are connected to data output pins.
Operations of the prior art semiconductor device tester will now be further described with reference to FIG.
1
. The tester
200
sends a control signal CON to a control signal input pin of the semiconductor device
100
through the control signal input driver amplifier
10
and further sends the control signal CON to the test pattern generator
30
. The test pattern reference data output from the test pattern generator
30
is then input to the semiconductor device
100
via the data input drivers
12
-
1
,
12
-
2
, . . . ,
12
-n connected to respective data input/output pins of the semiconductor device
100
. The semiconductor device
100
further outputs data corresponding to the input reference data test pattern on receipt of a control signal from the input driver
10
while the test pattern generator
30
outputs the reference data (or expected values). The respective amplifier gates
14
-
1
,
14
-
2
, . . . ,
14
-n in turn generate active signals when the voltage which is output through the corresponding input/output pins is higher than the high reference voltage (VOH). The amplifier gates
16
-
1
,
16
-
2
, . . . ,
16
-n respectively generate active signals when voltages output through the corresponding input/output pins are lower than the low voltage reference signal (VOL).
As used for purposes of the description herein an “active” state will be used interchangeably with a “high” or “set” state. Similarly, an “inactive” state will be used interchangeably with a “low” or “reset” state. However, it is to be understood that the present invention may equally be applied in circuits using what is commonly referred to as negative or inverse logic with the necessary changes to embodiments described herein being readily known to those of ordinary skill in the art.
As can be seen from the schematic block diagram of
FIG.1
, the AND gates
20
-
1
,
20
-
2
, . . . ,
20
-n respectively perform logical multiplications of the output signals of the corresponding amplifier gates
141
,
14
-
2
, . . . ,
14
-n and non-inverted levels output from the test pattern generator
30
, thereby generating high (active) signals when both inputs are at high levels. Similarly, the AND gates
22
-
1
,
22
-
2
, . . . ,
22
-n respectively perform logical multiplications on output signals from corresponding amplifier gates
16
-
1
,
16
-
2
, . . . ,
16
-n and signals from the test pattern generator
30
inverted by the inverters
18
-
1
,
18
-
22
, . . . ,
18
-n to thereby generate high level output signals when the signal from the test pattern generator
30
and the respective output pin of the semiconductor device
100
are both at a low level. Accordingly, the AND gates
20
-
1
,
20
-
2
, . . . ,
20
-n detect values of high levels output from corresponding data input/output pins of the semiconductor device
100
while the AND gates
22
-
1
,
22
-
2
, . . . ,
22
-n respectively detect values of low levels output from associated ones of the data input/output pins of the semiconductor device
100
. As a result, the OR gates
24
-
1
,
24
-
2
,
24
-n respectively generate high level signals when matched values of high levels are detected by the AND gates
20
-
1
,
20
-
2
, . . . ,
20
-n and when low level values are detected by the AND gates
22
-
1
,
22
-
2
, . . . ,
22
-n.
When the output signal of the OR gates
24
-
1
,
24
-
2
, . . . ,
24
n are at low levels, they are judged to be inferior and at high levels, they are judged to be normal. The AND gates
26
-
1
,
26
-
2
, . . . ,
26
-n, in turn, respectively perform logical multiplications on the signals COM EN generated by the test pattern generator
30
and the output signals from the OR gates
24
-
1
,
24
-
2
, . . . ,
24
-n to thereby generate a high or low level signal output. Finally, the D flip flops
28
-
1
,
28
-
2
, . . . ,
28
-n, responsive to strobe signals generated by the timing generator circuit
32
, generate output signals of the AND gates
26
-
1
,
26
-
2
, . . . ,
26
-n as the output signals OUT
1
, OUT
2
, . . . , OUT n respectively. In other words, the tester
200
generates output signals for the respective corresponding input/output pins of the semiconductor device
100
with reference to the high and low level voltage reference values VOH, VOL respectively at times defined by the strobe signal to discriminate whether there has been a state transition on the input/output pins at the time of the strobe signal.
This prior art semiconductor device tester design has various problems. The tester only determines whether there has been a transition of output data at a strobe signal controlled tim

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