Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With heat sink means
Reexamination Certificate
2001-03-30
2002-08-13
Ho, Hoai V. (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With heat sink means
C257S724000, C257S048000
Reexamination Certificate
active
06433410
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a tester for testing a semiconductor chip such as a bare chip or a package such as a narrow-pitched ball grid array to be mounted on a printed wiring board by face-down bonding. The invention relates further to a method of testing a semiconductor chip such as a bare chip or a package such as a narrow-pitched ball grid array to be mounted on a printed wiring board by face-down bonding.
2. Description of the Related Art
In these days, a semiconductor chip or a semiconductor package is generally mounted on a printed wiring board (PWB) by a face-down boding process which is one of wireless bonding processes.
In accordance with a face-down bonding process, since a connection terminal of a printed wiring board is positioned just below or in the vicinity of a semiconductor chip, it would be possible to mount semiconductor chips on a printed wiring board at a high density.
In addition, since a plurality of external terminals such as semiconductor chips can be bonded at a time, it would be possible to mount a plurality of semiconductor chips in a short period of time. Furthermore, since a semiconductor chip and a printed wiring board are positioned at a short distance to each other in a face-down bonding process, a face-down bonding process is suitable to a high-speed device.
As mentioned above, a face-down bonding process presents various advantages.
In general, a semiconductor chip or a semiconductor package to be mounted on a printed wiring board by a face-down bonding process is formed at a surface thereof with a plurality of externally projecting terminals at a high density. For instance, a bare chip or a ball grid array (BGA) including balls arranged at a narrow pitch is designed to include thousands of external terminals at a pitch of about 0.2 mm. It would be quite difficult to surely contact all of the external terminals to tester pins.
Hence, a test was conventionally made in order to merely guarantee a quality of a semiconductor chip, however, it was quite difficult or almost impossible to directly test a semiconductor chip as to whether a semiconductor chip could operate in a desired manner.
As a result, a semiconductor chip was tested as to whether it could operate in a desired manner, after the semiconductor chip was mounted on a printed wiring board. This test is called a card test.
FIG. 1
illustrates one of card tests, in which a bare chip mounted on a printed wiring board is tested by means of pins (hereinafter, a test as explained hereinbelow is called a pin type test).
In the pin type test, a bare chip
2
is mounted on a printed wiring board
10
.
Then, electrode pins
104
are caused to stand on electrode pads
103
formed on opposite surfaces of the printed wiring board
10
. Specifically, guide blocks to which the electrode pins
104
are fixed are compressed onto the printed wiring board
10
from opposite sides of the printed wiring board
10
to thereby ensure contact between the electrode pads
103
and the electrode pins
104
.
Then, a test signal is input into the bare chip
2
from the electrode pins
104
through the printed wiring board
10
, and subsequently, the test signal is picked out of the bare chip
2
to thereby test performances of the bare chip
2
.
However, it would be quite difficult to take a semiconductor chip out of a printed wiring board after the semiconductor chip has been once mounted on the printed wiring board by a face-down bonding process. Hence, if a semiconductor chip is found defective in the pin type test, not only the semiconductor chip but also the printed wiring board on which the semiconductor chip is mounted have to be scrapped together. This results in a problem of an increase in fabrication costs of a semiconductor chip and a printed wiring board on which a semiconductor chip is mounted.
In order to solve this problem, Japanese Unexamined Patent Publication No. 5-206227 has suggested a test socket as a test tool for testing a bare chip solely.
FIG. 2
illustrates a test socket
200
suggested in the Publication.
The test socket
200
is comprised of a container
210
, a cover
220
for sealing the container
210
therewith, a plurality of output pins
211
extending from an outer bottom of the container
210
, connection pads
212
mounted on an inner bottom of the container
210
in alignment with bumps
201
of a bare chip
2
to be tested, and an anisotropically electrically conductive sheet
203
mounted on the connection pads
212
.
The test socket
200
is mounted on a substrate under test (not illustrated) by soldering the output pins
211
onto pads mounted on the substrate under test.
The bare chip
2
is inserted into the container
210
such that the bumps
201
face the anisotropically electrically conductive sheet
203
. Thereafter, the container
210
is sealed with the cover
220
to thereby compress the bare chip
2
onto the anisotropically electrically conductive sheet
203
. Thus, the bumps
201
and the connection pads
212
are electrically connected to each other through the anisotropically electrically conductive sheet
203
.
Thus, in accordance with the test socket
200
suggested in the above-mentioned Publication, the bare chip
2
can be tested solely before being mounted on a printed wiring board. Hereinbelow, the test carried out by means of the test socket
200
is called a socket type test.
However, the above-mentioned socket type test is carried out in a condition quite different from a condition in which a semiconductor chip is actually mounted on a printed wiring board. As a result, even if a semiconductor chip were found non-defective in the socket type test, the semiconductor chip might be judged defective in the above-mentioned card test which is carried out after a semiconductor chip has been mounted on a printed wiring board.
Thus, the socket type test is accompanied with a problem of low reliability in results of testing a semiconductor chip.
For instance, in the socket type test, a transmission line through which a test signal is input into or output from the bare chip
2
becomes unavoidably longer by a length of the pin
211
. Hence, it would be impossible to test a semiconductor chip operating in a high rate with a radio-frequency signal being transmitted therefrom and received therein, with high reliability in the socket type test.
In addition, it is necessary in the socket type test to make the number and an arrangement pattern of the connection pads
212
coincide with the number and an arrangement pattern of the bumps
201
of the bare chip
2
. As a result, the test socket
200
can test merely semiconductor chips having the same number and arrangement pattern. Accordingly, when various kinds of semiconductor chips are to be tested, it would be necessary to prepare test sockets associated with those semiconductor chips, resulting in an increase in fabrication costs of a printed wiring board on which those semiconductor chips are to be mounted.
Furthermore, the test socket
200
is accompanied with a problem that it is not always ensured to cause the bumps
201
and connection pads
212
to make contact with each other through the anisotropically electrically conductive sheet
203
merely by sealing the container
210
with the cover
220
.
Specifically, it is generally necessary to apply a force of about 9.8×10
□2
N or greater per a bump to the bare chip
2
in order to ensure contact between the bumps
2
and the connection pads
212
. For instance, if the test socket
200
includes 4000 bumps
2
, it would be necessary to apply a force of about 392 N to the bare chip
2
. It would be quite difficult or almost impossible to uniformly apply such a great force to a semiconductor chip having an area of a few square centimeters, because the container
210
is closed merely by being compressed by the cover
220
which is connected to the container
210
through a hinge.
Japanese Unexamined Patent Publication No. 11-224915 has suggested a substrate on which a semiconductor bare chip
Fukasawa Yoshihito
Inoue Hirobumi
Ito Hiroo
Kimura Takahiro
Tanioka Michinobu
Ho Hoai V.
Huynh Andy
NEC Corporation
Whitham Curtis & Christofferson, PC
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