Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2006-10-24
2009-11-03
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S021000, C710S032000
Reexamination Certificate
active
07612578
ABSTRACT:
A semiconductor device, a test system and a method of testing an on die termination (ODT) circuit are disclosed. The semiconductor device includes an ODT circuit, a termination impedance control circuit and a boundary scan circuit. The termination impedance control circuit generates termination impedance control signals in response to a test mode command. The ODT circuit is coupled to the plurality of input/output pads and generates a plurality of termination impedances in response to the impedance control signals. The boundary scan circuit stores the termination impedances to output the stored termination impedances. Thus, the semiconductor device may test an ODT circuit accurately by using a smaller number of pins and may reduce a required time for testing the semiconductor device.
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Chang Young-Uk
Hwang Seok-Won
Hyun Dong-Ho
Mills & Onello LLP
Samsung Electronics Co,. Ltd.
Tabler Matthew C
Tan Vibol
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