Semiconductor device, tab tape for semiconductor device,...

Details Semiconductor device, tab tape for semiconductor device,... Semiconductor device, tab tape for semiconductor device,...

1998-07-29

2001-11-27

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S123000, C257S712000

Reexamination Certificate

active

06323058

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a tape automated bonding (hereinafter, referred to as TAB) tape used in the semiconductor device and, more particularly, to a semiconductor device of a chip scale package (hereinafter, referred to as CSP) structure and a structure of a TAB tape used in the semiconductor device.
In packaging of a semiconductor device, a semiconductor device of a conventional lead on chip structure is widely employed as a basic structure of a 16M DRAM and so on because of high density mounting capability and high design freedom of a semiconductor chip and a semiconductor device. However, a bonding pad of a semiconductor chip such as a large scale integrated semiconductor circuit and an inner lead of a semiconductor device lead frame are connected with a bonding wire such as a gold wire or the like. According to this connecting method, that is, the ball bonding method by heat pressing using the bonding wire such as the gold wire or the like, it is difficult to reduce the pitch between the bonding pads below 100 &mgr;m and accordingly to limit the wiring design because of limitations in the size of a heating tool which forms a ball in a top end of the bonding wire by heating and in the size of a tool such as a capillary which holds and moves the bonding wire and press-bonds the ball formed in the top end of the bonding wire to the bonding pad of the semiconductor chip.
Further, the connecting method between the bonding pad of the semiconductor chip such as a large scale integrated circuit or the like and the lead of the TAB tape in the conventional TAB is performed by forming a vamp made of gold or the like in the bonding pad of the semiconductor chip, and tinning the corresponding metal lead to be connected through a gold-tin alloy bonding method (refer to “VLSI packaging technology (the first volume)”, pp74-97, published by Nikkei PB Company). According to this method, it is possible to set the pitch between the bonding pads to 50 to 100 &mgr;m. However, since the vamps need to be formed in the pre-process of semiconductor pitch (micro-machining of the wafer), there are problems in addition of processes and in price of the semiconductor device. Therefore, the method is not suitable for being applied to a package containing a semiconductor chip like a large scale integrated circuit of small batch production such as an ASIC device.
A method of face down connecting a semiconductor chip such as a large scale integrated circuit onto a ceramic board or the like by providing solder vamps on a bonding pad of the semiconductor chip is applied to a mass production process as a high integrated mounting technology in a super-computer field (refer to “'97 Symposium on New Technology of VLSI packaging”, p126, held on Mar. 3-4, 1997, sponsored by the Society for Semiconductor Packaging Technology Study). This method has problems in that the solder bonding vamps need to be formed on the surface facing the semiconductor chip because the vamp pitch, that is, the bonding pitch, is as wide as approximately 250 &mgr;m, and in that the cost becomes high because an alumina ceramic material having a linear thermal expansion coefficient near the linear thermal expansion coefficient of the silicon substrate forming the large scale integrated circuit must be used in order to moderate thermal stress acting on the bonding portions. The reason why the vamp pitch in this method is as wide as approximately 250 &mgr;m is that making wiring formed on the ceramic substrate to be finer is more difficult than in the case of the TAB.
The semiconductor device
1
′ of a CSP structure called as &mgr;BGA (BGA: Ball Grid Array) structure, as shown in
FIG. 11
, developed by TESSERA Inc., has a structure in which solder balls
3
′ as externally connected members are arranged in a region inside the periphery of a semiconductor chip
2
′. According to this structure, as the size of the semiconductor chip
2
′ is decreased with progress of the micro-machining technology of the wafer, the pitch between the solder balls
3
′ as externally connected members needs to be reduced as shown in
FIG. 13
, as well as the pitch between bonding pads
4
′ of the semiconductor chip
2
′. However, there is a disadvantage in that when the pitch P between the solder balls
3
′ is decreased, compatibility among packages cannot be maintained and wiring design of a print board needs to be changed.
Since the &mgr;BGA is widely used as a structure of a semiconductor device for a potable apparatus such as a flash memory or the like, it is strongly required to reduce size and cost of the semiconductor chip. The most widely employed method of reducing cost of a semiconductor chip is a chip shrink technique in which the size of the semiconductor chip is decreased using the wafer micro-machining technology to increase the number of chips obtained from one single wafer.
FIG. 13
A shows a feature before the chip shrinking, and
FIG. 13
B shows a feature after the chip shrinking. Further, the &mgr;BGA structure developed by TESSERA Inc. has a disadvantage in that it is difficult to employ the chip shrink technique in connection with the &mgr;BGA structure because there is the above-mentioned problem when the size of the semiconductor chip is decreased.
Furthermore, in the above-mentioned &mgr;BGA structure, the TAB tape
5
′ used for the member to construct the package is formed by making holes in an insulator tape
6
′ member made of polyimide or the like through press-working. Therefore, there is a limitation in machining of the micro-holes because it is difficult to make the micro-holes having a diameter as small as the size of the bonding pad, and there is a problem in that when a TAB tape of a three-layer structure having a bond between a metallic film and the insulator tape is used, the press-working of the inside surface of the holes squeezes out the bond from bonded edge portions.
In addition to the above, in the above-mentioned &mgr;BGA structure, an elastomer
8
′ having a length of approximately 100 &mgr;m is arranged between the semiconductor chip
2
′ and the TAB tape
5
′ as a thermal stress modulating member. However, according to this structure, in order to connect a metallic film lead
7
′ of the TAB tape to the bonding pad
4
′ of the semiconductor chip
2
′, the lead
7
′ needs to be formed so as to have an S-shaped bent portion depending on a level difference to the bonding pad
4
′. In order to do so, a tool having a cross-shaped groove in the top end is used as the bonding tool for forming the lead in the S-shape to connect it. The lead
7
′ is bent toward the bonding pad
4
′ of the semiconductor chip
2
′ while the lead
7
′ is being held by the groove of the tool, and connected to the bonding pad by controlling so that the lead
7
′ is slightly moved in the horizontal direction to a desired position.
Therefore, from the problems caused from the structure and the operation of the bonding tool, it is difficult to bend and mold the lead
7
′ to be wired in a slanting direction, in the horizontal direction toward the bonding pad
4
′, and to connect to the bonding pad, in a case where the bonding pads
4
′ are arranged in the corners of the semiconductor chip
2
′, as shown in FIG.
12
. As a result, the bonding pads
4
′ cannot be arranged in the corners of the semiconductor chip
2
′, and accordingly it is difficult to decide the pitch between the bonding pads
4
′.
In addition to the above, in the above-mentioned &mgr;BGA structure, since the lead
7
′ to be connected to the bonding pad
4
′ of the semiconductor chip
2
′ in the TAB tape
5
′ is supported in a cantilever state from an edge portion of the insulator tape
6
′, the lead
7
′ itself needs to have a strength to a certain degree, and if not, there is caused a problem of strength

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